Daniel Y. Email & Phone Number

Chuo-ku, Tokyo, JP

Responsible for leading Woven by Toyota’s global operational safety and management of software safety initiatives- Establish and lead a company wide safety committee to ensure effective safety and risk management - Develop safety concepts with technology roadmap to support deployment of Woven by Toyota’s portfolio of advanced driving solutions- Provide.

Cambridge, Massachusetts, US

- Managed ISEE’s product compliance, and safety certification efforts- Developed safety concepts with technology roadmap to support deployment of ISEE’s portfolio of autonomous yard truck solutions- Engineered ISEE's safety principles (Safety by Design | Proven | Risk Informed | Trustworthy) into day-to-day tasks as part of the robust safety cases for.

Boston, Massachusetts, US

- Autonomy Safety Performance Metrics- Autonomy safety assurance - safe AV behaviors and interactions - System and Safety collaboration with commercial partners (Lyft and UberEats)- Lead safety engineer for Motional's Remote Vehicle Assist program- Lead safety engineer for Motional's next generation platform architecture

Boston, Massachusetts, US

- Lead author for Motional’s Autonomous Vehicle Safety Development Lifecycle processes and Safety Case Framework (UL 4600 informed)- Functional safety manager (ISO 26262) for Motional’s High Performance Compute (HPC) platform- Managed functional safety requirements and safety concept developments for Lidar, Radar, Camera, and IMU ECUs- SOTIF (ISO 21448).

San Francisco, California, US

• Managed system safety lifecycles for Uber's Self-Driving Enterprise
• ISO 26262 compliance for Self-Driving Vehicles’ Electrical/Electronic components and integrated systems: - Safety requirements development - Functional safety concept - Technical safety concept - Safety requirement V&V
• Facilitated process development for adopting ISO/PAS 21448 (SOTIF) for the self-driving platform
• Delivered system and module level safety analysis utilizing FHA, STPA, FTA, and FMEA
• Derived and managed Uber's Self-Driving Safety Case work plan in accordance with UL4600

Carlsbad, CA, US

• Managed a portfolio of Viasat’s Forward Error Correction (FEC) and wireless communication IPs
• Managed development activities for a Terabit Optical Transport Network ASIC/12 nm FinFET for cloud networking and data center applications
• Served as an operational excellence and continuous improvement champion for Viasat’s ASIC/FPGA development methodology

Amsterdam, Noord-Holland, NL

• Managed multiple installed base programs for Philips' Advanced Molecular Imaging (AMI) and Computed Tomography (CT) platforms
• Directed phases of product lifecycle management process. Led a team of project managers and cross-functional leads to support all aspects of medical device recalls (Post-Market Surveillance Program Management)
• Served as the main point of contact between Philips and the global regulatory agencies
• Led a software development program for Philips' AMI scanner with extensive dFMEA/pFMEA, and V&V activities

Boston, MA, US

• Neutron Scattering System Program Manager:
• Managed contract teams around the globe, including locations in the U.S., U.K., and Asia
• Directed system requirement management, design-to-cost tracking, verification & validation methodology, agency approval (EMI/EMC/Safety), user acceptance, and supply chain coordination
• Launched the world's highest performance Small Angle Neutron Scattering System (SANS) with Julich Center for Neutron Science (JCNS) in Munich, Germany
• Architected a modular and scalable Neuton/Gamma detection system platform based on the Xilinx Zynq FPGA with embedded Linux Operating System (OS)Neutron Imaging System Program Manager:
• Successful delivery of world's first turn key Small Angle Neutron Scattering System (SANS) to National Institute of Standards and Technology (NIST) in Maryland USA, and Australian Nuclear Science and Technology.

Bethesda, MD, US

• Engineering manager with 20 direct reports supporting multiple large scale development programs
• Responsible for horizontal integration, process definition, cross-functional planning, and manufacturing support
• Proposal author and principal investigator for several DARPA and NRL programs
• System requirements management, validation, and analysis
• Trade analysis in design methodology, tool set evaluation, and support for transition to production
• Responsible for leading new product development, design for test (DFT), design for assembly, risk mitigation, and cost management for manufacturing

Bethesda, MD, US

• Integrated Product Team (IPT) Lead:
• Automated Video Tracker system design and modeling (Matlab based)
• Design for test (DFT), design for manufacturing, and risk mitigation
• Xilinx Virtex 5 based hardware, firmware, and software co-development and integration

• First to market DVB (Digital Video Broadcast)-S2 compliant system
• Schematic design, including RF and mixed signal sections, for the DVB-S2 gateway transmitter
• Component selection, design for manufacturing, remote management, and field upgrade capability
• BCH and LDPC encoder and DVB-ASI design for the transmitter FPGA (Altera Stratix 1S-80)
• Gateway system and user terminals deployed across multiple teleports and regions worldwide for VoIP servicesMulti Rate Digital Modem for terrestrial wireless application
• Supports GigE, OC3/OC12, STM1/STM4, HD-SDI, in a modular design

Espoo, Southern Finland, FI

• Development of next generation Multi-Service/MPLS Edge Router chip set
• Developed functional and design specifications
• Performed resources allocation and schedule managements
• Coordinated efforts for hardware design, software development, co-verification, and diagnostics Development of 40G (OC-768c) IP/MPLS Core Router chip set (250 MHz @ 0.13um)
• Developed OC-768C MPLS/IP router system architecture, requirements, feature set, and functional specifications
• Developed and executed ASIC design plans including ASIC design process, system modeling, verification, and software co-development environment

Germantown, MD, US

• System on Chip (SoC) design for Hughes' next generation satellite gateway and set-top box
• Performed system and architectural design of a multi-million gate ASIC (100 MHz @ 0.18um)
• RTL coding, simulation, logic synthesis, test synthesis, static timing analysis, and formal verification
• Completed system verification and DFT insertion (full scan, JPEG, BIST, ATPG) for ASIC tape-out
• Converted an FPGA to a working ASIC for DirecTV set-top box chipset

Master'S Degree, Eecs

Bachelor'S Degree, Electrical Engineering