Manage the GaSb substrate operation from crystal pulling, post ingot processing to polishing.• Manage production plan, manufacturing issues, and personnel in the operation.• Work on process development to reduce crystal defects on GaSb ingots.• Develop internal polishing powder formulation and optimized final polishing process to reduce haze, particle, and scratches on epi ready substrate wafers.• Work on continuous process improvement to resolve current manufacturing issues and to improve processing yield, reduce cycle time, and meet product delivery goals.• Implement substrate wafer quality verification using various characterization tools and processes such as Ellipsometry, Interferometer, Surfscan, HRXRD, AFM, Hall, FTIR, and EPD.• Work with internal epitaxial growth group to trouble shoot current substrate wafer issues, and qualify new substrate processes and vendor changes.• Work with IT to implement substrate processing onto database.• Work with equipment vendor to resolve current equipment issues and make design modification for new equipment.• Work with chemical suppliers and other suppliers to resolve incoming material quality issues.• Experience with LEC crystal puller, ID saw, dicing saw, laser coring, wire saw, double side and single side polishers, and substrate chemical cleaning processes.

Worked on the R&D and the startup of GaSb substrate operation. • Developed and optimized the substrate wafer polishing process flow.• Identified vendor and work with the vendor to design the tooling needed for the equipment and processes to start up the operation.• Demonstrated super flat epi-ready GaSb substrate with flatness less than 5um on 4” GaSb wafer with ultra low surface oxide thickness.• Helped with the startup of the post ingot processing operation. Learned equipment operation and implemented the process flow for ID saw, dicing saw, and edge grinding.• Developed and wrote process travelers and standard operating procedures for the operation.• Managed daily production plan and manufacturing issues.

Worked with the product development of uncooled infrared focal plane array. (1) Managed the schedule, process, and issues related to a specific customer project. Introduced new product into manufacturing that meets the customer specification and provided technical customer support and communications to external customers. (2) Worked with the design group to modify the bolometer layout and test structure layout for each new product introduced into manufacturing. Reviewed layout prior to ordering masks. (3) Created process flow specifications for manufacturing for each new product introduced into manufacturing.(4) Worked with lithography group to perform focus exposure matrix for each new layout layer and determine the best lithography process for each layer. Worked with all other groups in manufacturing to make sure new processes and recipes are set up and ready for new product introduction.(5) Performed experiments with new processes that enhanced device performance while reducing the pixel size.(6) Investigated product yield issues and implemented new processes and procedures to improve yield.(7) Set up and measured the 1/f noise and TCR of uncooled infrared sensor structures.

Worked in HPL Technologies from June 2004 to Dec 2005, then joined Synopsys through acquisition. Worked under the testchip organization.Lead the circuit design and development of high density analog array testchips include the HD MOSFET array and HD via array. Worked on the circuit simulation, device sizing, design constraints, and de-embedding technique to enhance the accuracy of the extracted data from the circuit.Worked on individual circuit modules such as Opamp and BGR.Worked on the physical design of discrete parametric test structures for process characterization. Test structures worked on include MOSFETs, linewidth structures, resistors, capacitors, diodes, via chains, and combs.Implemented design with layout and schematic editors. Experienced with Mentor Graphics and Synopsys tools such as IC Station and Cosmos. Skillful in netlisting and simulation using HSPICE.

* Studied the photonic crystal distributed feedback laser. Involved in proposal writing.* Performed noise characterization on submicron size polysilicon-emitter bipolar transistors. Measured noise spectral density and extracted SPICE parameters AF and KF. Studied the noise mechanism and dependency on temperature, base current, and transistor geometry.