Responsible for processor core verification for ARM Cortex-A series processors (A57,A72, future cores). Developed unit level System Verilog/UVM testbenches for sub-units with an emphasis on register renaming and out of order issue/execution. Led effort for complete core pipeline (fetch, decode, rename, issue, execution, commit) verification via architectural level checking

Responsible for hardware verification across entire life cycle of products from high level design to hardware lab failure analysis for many generations of IBM Power and Z series systems. - Power8, Power7, Power6 Instruction fetch/decode unit verification team lead - responsible for leading international team developing and implementing verification plan for unit level verification of instruction fetch, instruction decode, branch prediction, and branch execution logic for processor core.- Power 5 Instruction fetch/decode unit verification team lead - responsible for leading team developing and implementing verification plan for unit level verification of instruction decode logic for processor core.- Power 4 Responsible for verification of processor core fixed point and floating point arithmetic functions- Z Series Assisted in various verification efforts on different projects with verifying elements of instruction issue unit, and with various elements of core level fault tolerance mechanisms.

Responsible for verification of frame relay card hardware and device driver running under real-time operating system, for a highly fault tolerant system designed for Motorola cellular systems. Developed testbench using C,C++, Perl running on real time operating system. Diagnosed device driver software and hardware problems.

Developed distributed fault tolerant transaction processing system across multiple platforms including Sun, SGI, Cray, IBM systems for government agency requiring SSBI clearance. Particular responsibilities included process and resource management control, primarily using C++ and Perl on unix platforms.