Started a Device, Product, and Test organization for an IP company working on a new carbon based memory technology. Designed and constructed test facility with bench and industry standard testers. Created test flows, methods, and database support for both single device testing and array level testing for carbon nanotube memory (type of ReRAM). Generated detailed operation and reliability characterization which drives process improvement and provides parameters for product design (EDR). Hosted domestic and foreign R&D executives & engineers for technology discussions – most of which are now in development projects for CNT memory based on information generated by my team. Transferred CNT memory technology to various fabs around the world.

Patents : 49 granted , more in progressSpansion LLC , 6-1988 – August 2008: Responsible for an organization that performs algorithm development, Flash memory technology characterization, and built-in-self-test (BIST) definition for use in Spansion’s Mirrorbit (virtual ground SONOS) nitride charge storage products. Lead team which worked with circuit design to define the chip architecture, redundancy, test modes, models, and MCU (8051 & ARM) functions. Our role required that we drive the performance and reliability parameters as well as ensure cost targets were met. Lead team in the original Mirrorbit development project and played a key role in the circuit design evolution that resulted in both the NOR and ORNAND product lines. Most of the patents for circuit design, architecture, and operation conditions show my involvement. Key leader involved in the process technology development and debug (ie: my team wrote most of the EDR’s and chip architecture rules). We use the technology test vehicle to match process performance to circuit design, yield, and marketing requirements. My group defines and generates the complex software that is used for sort as well as process characterization and optimization. Our software tools require self adjusting methods that are deterministic based on local level behavior. These smart tools are used to quickly setup and track electrical conditions temperature and transistor parameters. We have incorporated this deterministic approach into our products using BIST which determines custom optimal conditions for each die. These BIST modes are used to replace the sort flows for our product lines using a limited pin interface. We provide BIST interface requirements and detailed flow charts to design including variables, repair logic, and programmable test flows. The BIST and testmode responsibility requires us to be involved and engaged in the entire lifecycle of a technology from design to full production.

AMD : Product Line Manager (13 years)I was responsible for EPROM and Flash cost reductions, foundry startup & support, and product engineering operations. I was responsible for defining die shrinks including generation of GDR & EDR’s, chops, layout, circuit debug, testing, and qualification.

I was responsible for process integration on several micro controllers (8051, 8052), dual port SRAM, and EPROM circuits. Generated wafer process flows and specs. Tracked wafer electrical test parameters and correlated them to yield and process parameters. Created a yield prediction model based on critical dimensions and transistor VT. Also worked on establishing a bitmap & wafermap project for the EPROM which resulted in mask making and process margin corrections.

Managed two device measurement lab, designed and layed-out test chips for stepper characterization, process integration for miltary SONOS devices & SRAM's, and drove SPC software systems.