Darrell Davis Email & Phone Number

Senior Hardware Designer responsible for Component Selection, Digital/Analog Design, Schematic Capture, Supervise Layout, Simulation(Analog, Digital, Signal Integrity), Regulatory Approvals, Testing and Reporting. Interfacing with down steam groups including DSP, Software, Mechanical design, Manufacturing and Assembly. Documentation included SLAD (System Level Analysis Doc), DFE (Design For Environment), Hardware Description, Test Plan, Layout specification. Conduct design review with peers and Manufacturing reviews (DFM) with CM. My Role also included supervising and working with external contractors.Product Support. This would include, travel to customer sites to resolve issues, dealing with CMs, Reviewing DOAs and improve yields.My role included extensive embedded and software coding (ASM[ARM, MIPS, PIC], C/C++, Visual Studio, Visual Basic). Development Lead responsibilities included the following product definition, project budgeting, scheduling, Status updates to senior management, product costing, managing team members and resolving all issues that might arise during the project. Issues could include Mechanical design, Manufacturing and out sourcing. Dealing with contractors including writing statements of work, writing process required Docs such as SR&ED, Planning and Assumptions, and Issues and decisions doc.

Superset 4090 at Mitel NetworksThis was Mitel version of a Cordless Phone 900Mhz range. It interfaced to the Mitel DINC PBX. ACES for Defense research establishment Ottawa(DREO).Hardware Design of three VME 6 U cards. These cards were used to eavesdrop on any battle field communication and record it for later analysis. This design include three FPGA design one per card.Data Tap DREO.Hardware Design of a card that was used to tap into the radar system of F-18 fighters. The captured radars data was then stored for later analysis. A FPGA design by me served as the controller of this card.Lockheed Martin Light Ship Passive radar id system.Hardware and layout designer. FPGA design as well.