Darshan Umesh Email & Phone Number

Bengaluru, Ka, In

Bengaluru, Karnataka, India

• Technology: 40nm, Macro Count: 34, Standard cell count: 38403, Supply voltage: 1.1V, Power Budget: 600mW, Clock frequency: 833MHz, IR drop: (VDD+VSS): 5%.• Designing a Floorplan by determining macro placement as per dataflow diagram, and fly lines, and using the macro guidelines in order to achieve contiguous core area and good utilization.• Building a Power plan to maintain power network connectivity and IR drop. Also ensuring that there were no missing vias, floating wires, or power-ground DRC violations.• Creating a placement block by inserting pre-placement cells, placement constraints, and sufficient spacings in order to control the congestion and DRC violations obtained.• Performing clock tree synthesis and optimization using classic, CCD flows and analyzing the tool's behavior by comparing the timing reports in both flows.• Rectifying the LVS errors like shorts which were obtained post-routing by removing the overlapped routes and doing manual routing wherever necessary.• Analyzing and resolving the antenna violations by inserting the metal jumper and the diode into the layout.• Understanding the timing reports at every stage of PD flow, finding the cause of timing violations, and how some of the violated paths are being reduced in later stages.

Master Of Technology - Mtech, Microelectronics

Bachelor Of Engineering - Be, Electrical, Electronics And Communications Engineering