Darshik Mehta Email & Phone Number

Seattle, WA, US

Irvine, CA, US

• Designed and developed the Fault Management framework from scratch using C++. It is a modular, light weight, YAML config-driven and highly scalable service; which integrates thousands of system-wide faults reported by.
• Built the Framework APIs which are 'easy-to-use' by client applications. Incorporated Bazel auto generation capabilities for building the Framework using PyYAML translation modules that convert the YAML config to.
• Enhanced diagnostic routines by implementing multi-threading to perform parallel calibration of cameras which significantly improved the “takt time” for factory workflows. Collaborated with several cross-functional.
• Developed real-time features for the Driver Monitoring Systems (DMS) application running on QNX. Built a data-pipeline to feed vehicle/camera signals to the neural-net and distribute neural-net inferenced attributes.
• Optimized DMS camera start-up sequence for a quicker response time to comply with the privacy requirements.

San Jose, CA, US

• Developed data-driven, modular code in C++ for generating device configuration (such as device images and bitstreams applicable to Versal ACAP) in Vivado. (Vivado is the FPGA-design implementation software tool to.
• Achieved ~20% gain in the run-time performance of the legacy bitstream generation flow (applicable to UltraScale/UltraScale+) by improving the multi-threaded implementation in OpenMP.
• Developed and owned feature implementation for the SEM (soft-error mitigation) solution in Versal.
• Implemented a test-utility for dev-testing of bitstream configuration. Extended it to a regression suite to detect changes introduced by the cross-functional partners to distinguish between the bitstream-dependent.

San Jose, California, US

• Developed system software features and modules for IQNOS (Infinera's proprietary software OS).
• Designed and implemented platform-independent application code for the Yang-based data model architecture. Improved the software interface of the DSP-Driver which sits between the MCU (controller) and the Firmware (DSP).
• Automated the process of packaging Firmware binaries in SW Builds. Managed maintenance activities in Perforce – code migration, merge and integration for Dev and Release branches.
• Provided troubleshooting/debugging support and resolved software issues encountered during field-setups of the XTS-3300 (Gen4) product.

Palo Alto, California, US

• Setup and automated the flow of Ansys’s Totem tool by writing Perl wrappers in Unix development environment.
• Performed cell characterization and HSPICE simulations to model the CAD flow for the accuracy of signal and power EM/IR analysis.
• Generated pre-routes for an IP block with an internal place-and-route tool.
• Provided additional support for Perl scripting for Verilog-based scan-trace flows.

Palo Alto, California, US

• Responsible for full-custom layout design of multi-ported register file memories in 16 nm tech-node for Broadcom's Central Engineering division.
• Chiefly responsible for the layout design of memory bit-cells used in general purpose register file (10r5w, 4r4w configurations) inclusive of floor-planning, routing and decision-making of choosing metal layers for the.
• Gained macro-level design experience by designing leaf level cells, improving performance and timing by optimizing block-level design and placement, delivering design Library Exchange Format (LEF).
• Gained broad experience over various tech-nodes for the design and development of standard cell libraries in 130nm, 28nm, 20nm and 16nm.
• Familiarity with semi-conductor processing technologies, the electrical circuit characteristics and layout constraints pertaining to the FinFET fabrication processes.
• Assisted design team with characterization of design, parasitic extractions, planning for IR-drops, electro-migration, QA.

Master Of Science, Computer Engineering

Bachelor Of Engineering, Electronics