Sai Sneha Dasari Email & Phone Number

Santa Clara, Ca, Us

Santa Clara, Ca, Us

San Jose, Ca, Us

• Experience in timing constraints development and debug for multi corner, multi-mode design.• Drove the full chip timing closure along with signal integrity convergence (cross talk and noise) on 7nm, low-power, design projects for FPGA and ACAP devices at multiple timing corners and multiple modes using the latest timing flows and methodologies.• Successfully converged on Full Chip Timing Sign off, DRV, Crosstalk & Noise for a critical NOC (Network on Chip), with complex clocking structure having 1500 clocks.• Owned Boundary SCAN, IJTAG timing analysis for multiple devices.• Achieved Timing closure with tight correlation to Place and route tools ensuring minimal disturbances in layout.• Worked on STA constraints validation and verification assisting tool features like, constraints linting, constraints verification, constraints generation, hierarchical consistency checks, hierarchical constraints propagation and integration, and multimode coverage analysis.

• Synopsys Certified trainer for delivering multiple CES in Prime Time to prominent Semiconductor giants like Intel, Qualcomm • Devised an implementation strategy to overcome tool’s inherent limitation to optimize the discrete Latch-based Clock gating structures, to Library-based ICG (Integrated Clock gate cell) (spanning all types of possible latch based ICG’s including AND, OR type with pre and post latch control pins) in Design Complier.• Successfully mitigated congestion (5% -> 0.02%) on a networking chip block implemented on 16FF technology node.• Proficient in the use of Prime Time (Synopsys) tool and TCL scripting.• Collaborate with key customers to develop, optimize, automate, and deploy advanced timing analysis & sign-off solutions like MIS, DMSA, SMVA, etc.• Worked on advanced Prime Time features and Signoff methodologies for 7nm multi-hierarchy, low-power complex designs• Devised a Clock ECO methodology to perform slack recovery on simultaneous setup and hold timing critical paths wherein hold timing was met without any degradation in setup. The algorithm strategy involved removal of inverter pairs from the capture path, addition of inverter pairs in the launch path for hold critical paths, thus making sure, that no new setup violations were created, aiding to achieve the target QOR frequency of 1.4GHz for an RFIC chip.

• Developed advanced methodologies and flow improvement strategies to achieve the best power, performance, and area for 5M+ instances block.• Worked in collaboration with R&D to connect customer’s requirement for tool enhancement and new feature development, thereby enhancing the scalability of the tool.• Collaborated on automation and enhancement of a timing ECO flow• In addition to Full flat STA flow, worked extensively on Hierarchical STA flows such as Extracted Timing Model (ETM) incorporated flow, Hyperscale flow to help reduce resources and runtime.• Responsible for the diagnosis, resolution, and drive closure of reported design signoff problems from multiple projects and customers.

Master Of Engineering - Meng, Vlsi Design

Bachelor Of Technology - Btech, Electrical, Electronics And Communications Engineering