Architect for DV AI Transformation Optimization

. Led Global Test Screens Verification and Review (U.S, Shanghai, Malaysia, India PE teams). Managed +600 screens review yearly. Deep dive special review on DFT (design for test) test screens, peripheral stress and all OEM RMA failure screens for DDPM improvement with minimal yield loss. . Program manager to implement internal trade secret “Universal python test code” to be used in different in-house bench testers.. Program manager to implement internal trade secret to improve 3-4% factory production high stack die package test yield loss.. Program manager for automation on Test process, Test program checkout, Test program Release. Leading innovation for test process, test equipment cost savings, salvage production test failure units for re-sale. . Led engineering in U.S. and Asia to support 4 years cost saving of $200M by improving each 0.05% test block yield loss.. Successfully improved Raw Nand yield for multi-die (8D/16D) package from 90%/92% to 97%/99% by hands on FA with factory team on ZQ calibration test and DDR speed test. That saved +$ 20M for high-speed testers purchases.. Yield improvement, OEM product DPPM improvement using AI technique and shift-left method to feedback all true failure modes to Fab for solution.

2011-2018. Led Nand product engineering team with 40+ engineers and 5 managers supporting multiple OEM product lines (Mobile and Client Computing; AWS, Sony, Huawei…) and FA team for RMA failure analysis and test screen solution. Responsible for all Nand component testing for product development and production +$2B revenue. Led Nand component product test development for all product lines (e.g., LGA 52 first package for Apple smart phone qualification, Nand BGA package for SSD G5/G5 43nm/32nm, internal product lines…). PLCT PE lead, for high volume smart phone products. Review, planning resources for new projects. Responsible for Nand component final tested for customer samples, EVT, DVT qualification.. Support all PLCT/PDT activities for all OEM product lines.. Weekly updates to SVP for product development status and factory production yields and commit Meet or Exceed AOP yield and test time projection.. Defined roadmaps and schedules, prioritized new product development activities in the team. Pulling resources between teams to support business pulling schedule.. Define and discuss test specs with customers (BB allowance, Write/Read performance, unique ID defined…). Handling product engineering system map for PETE organization.Accomplishments:. Successfully led development team to qualify first Nand LGA52 43nm to Apple mobile (2011), first PPN product 2012 (~100M units shipped) followed up with new technologies ...1Y, 1Znm, BICS2, BiCS3). Delivered smallest PPN package for smart watch. Customers rating SanDisk Nand flash quality # 1 out of 5 vendors in several quarters from 2012-2013. Provided complete wafer to package test solution with aggressive ramp up schedule resulting in +$300M revenue for Mobile and Client Computing products in 2012.. Reclaimed test rejected die to retail products (e.g., USB…) 450PB 2014, 900PB 2015. . Hired and Built a product engineering team in India 2014 . Delivered first EX3 technology die to smart phone product.

. Manage PE team to initiate, develop test program, test process for product qualification for 2bit, 3bit, 4bit NAND technologies.. Lead development activities to provide good, tested Nand for new form factors memory (SD, uSD, M2, Memory Stick…) . Manage JIRA system to lock and track all key COEM failures and screens.. Nand device operation, functioning training for Milpitas/SDSS/UTC product engineers.. Leading yield improvement, test time reduction process for Asia factories. Improving yield from LVM 94% for 8D package to HVM 98% at factory. Built product engineering team in Shanghai to support new factory. Hired engineers, Nand technical training, test process training, agile documents for all product test development and mass production.. Hosting weekly meetings with oversea teams to follow up technical issues, projects status, providing feedback suggestions for technical solutions. Weekly updates product development status and yield result to VP. Improved more process of recovery failing die at wafer level test and downgrade it to lower grade retails products for re-sale saving ~$20M quarterly.

. New Product Development (NPI) for multiple product lines (CF, uSD, SD, Memory Stick). Technical Manager to manage Nand Flash team to bring up various product lines (Tsop/uSD/SDSip/BGA/LGA) from qualification to mass production of new technologies 70nm/56nm/43nm/32nm. Providing engineering support to qualify X3 technology to production.. Manage PE team to handle all technical issues for Qual/EVT/DVT RMA customer return failures.. Leading Yield improvement, Test time reduction, Salvage failing package downgrading to lower grade products (e.g., retails), saving ~$10-12M quarterly. . Leading team to bring up new production testers to support volume production ramp up.

. Manage JEC’s team and coded all SanDisk DAT (Device Approval Test) characterization test programs for 2D NAND 0.16 um, 0.13um, 90nm, 70nm, 56nm. Characterize DR (Data Retention), PD (Program Disturb), RD (Read Disturb), OP (Over Program) and Performance Program, Read, Erase speed. Developed post process macro/scripts to analyze the data. This is a tremendous contribution to Nand Flash Toshiba-SanDisk partnership. . Failure analysis on outlier fail die, package and feedback to Device and Process teams.. Innovating “Random pattern” with control for NAND Cell characterizing when technology shrinks to 56nm which could not pass with traditional CB/CBB patterns.. New Tester specification planning with Vendor, working with procurement team for new tester equipment purchasing to support larger Nand Chip

Team lead to support SanDisk first oversea production test houses at SPIL, AMCOR using MT98 tester. Lead all Asia Subcon product engineers to support all MT programs and production issues especially in first ever $100M quarter revenue. Developed remote-access automation application to handle test program release to Asia Subcon test houses from SanDisk Milpitas. Developed various application tools to support yield analysis, tester utilization, automate tester firmware update… Those automation tools were huge cost saving by reducing test program release time from 1 week (floppy disk sending out by UPS) to less than a day. This helped to control, FA and solve most of Asia Subcon production test issues from SanDisk headquarters.

New Product development, qualification for NOR 64 Mb, 80 Mb, 128Mb. Package component test, Product yield improvement, customer return failure analysis, update new screens and release to SanDisk Milpitas production.

. Product Engineer to support new product development Pentium II Microprocessor 266MHz, 300MHz. . Vector patterns project lead to convert all current production patterns from assembly codes to Schlumbeger tester format to support testing new product Pentium II. Automation process for team members to submit their pattern converters to different Sun OS servers. Failure analysis on failed patterns to provide failing wave forms to design team using Schlumbeger timing and pattern tools. Provide non-production patterns (Reserved patterns in the pool) to catch fail units returned from customer