Developing ASIC design methodologies for hierarchical and top-down physical synthesis, formal verification and ECO.• Developed automation software using PERL, Python, to run multiple combination of recipes for user specified designs (smart reporting, queue/disk management, ML based data analysis and recipe combo selection), achieving better TAT• Improved Fusion Compiler physical synthesis flow for Arm Hercules Core using combination of tool features and developed state-of-the-art methods, achieving aggressive WNS/TNS goals and better correlation with PnR• Developed single-session hierarchical synthesis flow with Fusion Compiler showing better QoR for critical designs• Developed timing-optimization methods using TCL (low-vt swap, timing driven ungrouping, net layer promotion, WNS driven useful-skew, critical CG replication)• Developed ECO methods using TCL (WNS driven useful-skew posts-PnR, ECO change-list translator)• Developed utilities for QoR data analysis (heat-maps, hierarchical timing report, timing-paths data statistics)• Developed utilities using TCL for formal verification with Formality

Developed EDA tools for Memory/IP Built-In Self-Test and Repair (BIST/BIRA) ASIC verification and failure diagnostics. Was responsible for Verification Environment Generator.• Added IJTAG (JTAG 1687) and IEEE1500 support to Verification Environment Generator.• Implemented E-fuse memory data preload file generation feature for fuse memory initialization.• Implemented BIST diagnostics chain dynamic parsing, reducing test time for passing simulations by order of magnitude.• Developed multi-TAP design RTL model, added support for the same to Verification Environment Generator.• Reduced Verilog/WGL/STIL simulation time by 20-40% by utilizing IJTAG functionality.• Developed a feature for external data file read during Verilog simulation, helping to avoiding Verilog recompilation.• Regression and manual testing using TCL.• Customer meetings, discussions, new feature presentation.• Product release management (SAP CRM), version control (Perforce), code reviews (Code Collaborator)Using:• C/C++, STL, Qt, TCL, Bash• Verilog/System Verilog• MS Visual Studio (2008/2013)

Developed custom circuits (schematic and layout) for DDR PHY for 65nm – 20nm technologies. Was responsible for self-calibrating digital delay line (DDL) and std-cell library development, parasitic extraction, spice simulation.• Improved DFF cells metastability, setup/hold times.• Developed incremental delay-step delay line cells.• Developed automation software using Perl, TCL/Tk, to run different PVT parallel simulations, generate HTML report. • Developed Verilog – HSIM/Hspice co-simulation flow for DDL equivalence and functionality checks.

Development of fitness and medical devices for human vital signs (PPG, Heart Rate, Respiration Rate, SPO2, Blood Pressure) and fitness (step count, calories, activity, body position) monitoring.• Developed step count tracking, body position recognition, activity monitoring, burned calories calculation algorithms using accelerometer, gyroscope, LabView, C++• Developed PPG signal processing based SPO2 calculation algorithm using LabView• Participated in PPG signal processing based Heart Rate and Respiration Rate calculation algorithms development• Developed application specific IIR and FIR filters, averaging algorithms, signal conditioning with LabView• Developed LabView environment for accelerometer, gyroscope data acquisition, real time data analysis/testing, algorithm verification, regression testing