David Savory Email & Phone Number

Boise, Idaho, Us

I'm looking to contribute to a company's success in SSDs or other electronic systems. I have strong experience in designing and debugging HW and HW+FW embedded processor systems ranging from DSP Audio spectrum analyzers to cellular handset chipsets to FPGA implementations of CATV headsets to storage products to GB ethernet products. My broad experience base supports the ability to work interactively with ASIC, HW and FW teams to identify and resolve system-level problems, as well as performing detailed HW design work. Experience on engineering teams both large and small, and program / project teams allows me to contribute to engineering process definition and enhancement, and productive interaction with senior management, program management, and customers.

Milpitas, California, Us

Milpitas, California, Us

San Jose, California, Us

Supported change of GB Ethernet IP core in company's existing design. Successfully coded and verified new core interface, frame-sync, statistics gathering and controlled error generation logic. Required learning existing design, company development environment, and relevant IEEE standards (802.3).

Fremont, Ca, Us

Working team lead for SSD FA. Contributed to FA of SSDs of various protocols. Built a reporting and status system to provide near-real-time status of all SSDs in FA, using a hybrid of Gsuite tools, EDW database reporting tools, and Seagate's custom HDD FA tracking system.

Fremont, Ca, Us

Oversee and direct a five-member engineer team in designing, debugging, and verifying SI of company SSD products. Managed interaction and communication with remote team in India, including coordinating and monitoring SI/PI analysis processes. Conduct extensive SI analysis of NAND and DRAM interfaces in SSD designs. Collaborate with technical team and senior leaders to develop and implement current, annual, and long-term technical, schedule, quality, business, and financial objectives. Develop strategies and operational practices to ensure team adequately supporting other departments. Identify training and developmental needs. Identified source of PCIe RX errors on LSI SSD with SI analysis in time to spin PCB without impacting production date.

San Jose, Ca, Us

Led a five-member engineer team in performing system HW validation of SSD reference designs based on LSI (Sandforce) controllers. Managed development initiatives for industry leading SSD controller, expanding over multiple sites. Directed design process definition for LSI SSD reference designs and interfaced between system HW design/SF3700 ASIC design teams. Designed uC HW and FW implementation of SATA DEVSLEEP protocol in LSI Pro-based drives.Defined NAND SI analysis flow and full-drive power supply simulation flow.Spearheaded team effort to implement schematic and Pspice simulation flows for LSI SSD designs, saving three PCB spins in the first year of use.

San Jose, Ca, Us

Coordinated conceptual design of platform for Agere read-channel IP validation and SW development and evaluation while leading design of FPGA-based ASIC emulation hardware for SW development and validation of Agere hard-disk controllers. Directed development of Agere/LSI BluOnyx portable wireless storage/media server product. Applied ASIC or FPGA place and route tools to create design implementations.Served in applications engineering role for portable media player ASIC product, including customer-facing functions, requirements definition, and validation planning.Guided team in realizing FPGA implementation of HDD controller, allowing pre-silicon firmware development and saving six months in reaching customer HDD production ramp.

Managed a three-member engineer team in port of automotive handsfree application from TI to Agere DSP platform and new platform testing. Served in a hands-on technical lead with customer-facing functions. Guided team to port full automotive speakerphone implementation from TI DSP in C code to Agere DSP in assembly code in just four months from start to final in-car tuning.

Completed FPGA design and verification and firmware development. Acted in a hands-on leadership role in FPGA and C-code development and in diverse application spaces.Contracted to Xilinx to lead several of their 3- and 4-day FPGA training classes at multiple locations.

Holmdel, New Jersey, Us

Applications and tools engineer for AT&T, then Lucent Technologies DSP product line. Factory apps support and HW tools design for DSP16A & CSP product lines. Then Tier 1 customer apps engineer for AT&T Cellphone Chipset. Major accomplishments included breakthrough insights on complex problems enabling customer production to continue at multiple Tier 1 customer sites.

One of two electrical design engineers for the Kay Elemetrics Sonograph DSP5500. This was the first voiceprint machine to use DSP instead of analog filtering to transform digitized sound into the 3-D time / frequency / intensity plot format used for voiceprints. Introduced at ICASSP in 1987 the DSP5500 was a breakthrough machine at the time, producing real-time voice print displays on a CRT monitor as the user spoke into a microphone. I and one other young engineer designed all of the circuitry and wrote all of the code for this 3-processor machine (MC68000 Main processor and 2x TMS32020 DSP processors). I was responsible for all of the DSP in the box including the filtering and FFT processing on the 32020 chips and a micro-coded decimating FIR filter based on a MAC chip for capturing at different frequency ranges. See http://jproc.ca/rrp/sonagraph_dsp5500.html