Dave Broughton Email & Phone Number

Kirkland, Wa, Us

Kirkland, Wa, Us

Tacoma, Wa

Retired Independent circuit design and layout engineer. Extremely knowledgeable integrated circuit design engineer form concept to silicon validation. Currently interested in emphasizing the physical design of RF/Analog integrated circuits. Experience in Cadence Virtuosos, Layout, LayoutXL, Spectre, SpectreRF and Mentor Graphics Calibre physical design verification.

Tacoma, Wa

Started working for Jet City Electronics which was bought out by Fox Electronics in 2008 which was bought out by Integrated Device Technologies in 2012.Worked on the Fox Electronics Xpresso/Xpresso Ultra and the LCXC products doing design, layout, verification, and initial product testing.Design: CMOS, LVDS and HCSL output buffers; phase detectors; active charge pumps, resistive charge pumps, passive loop filters, active loop filters, test die, verilog modeling of the on chip… Show more Started working for Jet City Electronics which was bought out by Fox Electronics in 2008 which was bought out by Integrated Device Technologies in 2012.Worked on the Fox Electronics Xpresso/Xpresso Ultra and the LCXC products doing design, layout, verification, and initial product testing.Design: CMOS, LVDS and HCSL output buffers; phase detectors; active charge pumps, resistive charge pumps, passive loop filters, active loop filters, test die, verilog modeling of the on chip programmable memory.Layout: proficient in both Virtuoso layout and layoutXL, physical layout of all the circuits I designed, top level layout, ESD protection circuitry, Mentor Graphics Calibre verification. Proficient in layout technics to minimize process and device variations, like common centroid, interdigitation and dummy devices.Product testing: wafer probe and assembled part testing using RF oscilloscopes, spectrum analyses, oscilloscopes, and other support electronics.With another design engineer handled all the computer support for Linux, Microsoft and Apple equipment. Including computers, routers, wireless routers, switches, VPN and software licensing.. Show less

Federal Way, Wa

2006 – 2008 National Semiconductor Corp. - Federal Way, WA Engineering Project Manager – Interface Manage projects from concept to production. Tasks include schedules, business case, phase reviews, resource assignments, team meetings.2004 – 2006 National Semiconductor Corp. - Federal Way, WA Principal Design Engineer – Interface Participated in the design and development of signal conditioning chips.• Designed a 4Gbps dual mux buffer chip with input equalization and… Show more 2006 – 2008 National Semiconductor Corp. - Federal Way, WA Engineering Project Manager – Interface Manage projects from concept to production. Tasks include schedules, business case, phase reviews, resource assignments, team meetings.2004 – 2006 National Semiconductor Corp. - Federal Way, WA Principal Design Engineer – Interface Participated in the design and development of signal conditioning chips.• Designed a 4Gbps dual mux buffer chip with input equalization and output pre-emphasis using Nationals BiCMOS8i process for use in high speed back planes.• Designed a 4.25Gbps quad buffer repeater with input equalization and output pre-emphasis using National’s BiCMOS8i process for use in high speed back planes and in data cables (Ethernet, etc…)• Supervised engineers designing follow on chips to the 4.25Gbps buffer repeater chip. Chips included a single mux buffer chip and a 2 x 2 cross point switch.1998 – 2004 National Semiconductor Corp. - Federal Way, WA Principal Design Engineer – RF Products Group Participated in the design and development of the Platinum Series Phase Lock Loops (PLL). • Designed 3 single (RF) and 4 dual (RF and IF) PLL's with both integer and fractional architectures. They were designed on Nationals AbiC 5 0.5um BiCMOS process operating at up to 3GHz. Each design improved on the various PLL specs including phase noise, spurious noise, lock time, and input sensitivity.• I was a team member on several transceiver projects helping in the PLL portion of the design.• Wrote numerous Skill and Perl scripts to help automate design tasks. Including a Skill parasitic capacitance back annotation program, a Perl parasitic calculation program, a Perl parameterized XOR rule generator, a Perl VCO parameter calculator, a Perl model parameter comparison program, Skill jitter function routines and a Skill oxide breakdown violation program.• Designed a 4Gb/s mux/buffer chip for use in high speed back planes. Show less

Federal Way, Wa

Participated in the design of a 3D graphics chip.• Designed a PLL for the chip's clock distribution.• Wrote Perl scripts to automate various steps in assembling the chip. Including place and route, back end verification, and HSPICE simulation.

Federal Way, Wa

A team member on the design and layout of several large CMOS and BiCMOS high speed SRAM's. I was responsible for all stages of the design from initial customer contacts through silicon evaluation. Tasks included review of customer specs, project schedules, detailed documentation and working with many fab processes (BiCMOS and CMOS), • 1M and 4M SRAM's, 5ns to 1ns access times.• Several embedded SRAM's • Worked on a SRAM complier• EEPROM's• Timing generator chip.• Wrote… Show more A team member on the design and layout of several large CMOS and BiCMOS high speed SRAM's. I was responsible for all stages of the design from initial customer contacts through silicon evaluation. Tasks included review of customer specs, project schedules, detailed documentation and working with many fab processes (BiCMOS and CMOS), • 1M and 4M SRAM's, 5ns to 1ns access times.• Several embedded SRAM's • Worked on a SRAM complier• EEPROM's• Timing generator chip.• Wrote small C programs to help automate design tasks. Show less

Puyallup, Wa

Participated in the development of 2.0 and 0.8um ECL standard cell libraries. I designed standard cells, wrote DRC and LVS rules files, assisted customers with chip designs, helped in the definition and implementation of a power bus analysis program.

Sunnyvale, Ca

Participated in the start-up of a digital GaAs group. Designed an eight bit mux/demux chip set. Set up the CAD system. Supervised a junior engineer and mask designers.

Cupertino, Ca

Participated in the design of an ECL gate array library. Designed and characterized cells, designed embedded SRAM's and helped in defining in-house CAD tools.

Sunnyvale, Ca

Designed an ECL 4-bit microprocessor, ECL 8 bit bi-directional buffer and an ECL16x4 bit 2 port RAM. I was a team member on an ECL 16-bit microprocessor design. I supported several TTL parts.