Dave Bush Email & Phone Number

Ottawa, Canada Area

Wind River has been long known as embedded OS company. Its flagship product is VxWorks, an RTOS that is deployed in over a billion devices. During my time at Wind River I’ve designed and implemented software on both VxWorks and Linux spanning a wide variety of networking and other technologies. The following are some of the product developments I’ve contributed to during my time at Wind River:Designed and implemented device software for IA, Quark and ARM based platforms for Wind River’s first Internet of Things offering - Helix Device Cloud. Authored high level design documents and vetted designs with system architects. Portable solution written to execute both on VxWorks and Linux. Our solution is one of the winners at the 2014 M2M Evolution IoT Excellence Award.Intelligent Network Platform (INP) is a solution designed to provide a fast datapath that can accelerate forwarding and termination many times faster than native linux. INP is a linux user space application that provides an accelerated datapath for L3/L4 protocols using DPDK.Integrated an INP deployment into Wind River’s Titanium server platform to be used in NFV applications. Implemented IPsec offload to an Intel Cave Creak offload processor with Intel’s Quick Assist driver. Implemented multiple performance enhancements to achieve maximum throughput by writing an adaptive kick/poll algorithm. Implemented code in various other areas of this technology, solved many defects and performed performance measurements for L3/L4 forwarding and termination.Wifi driver support for VxWorks. Integrated broadcom driver with WPA, WPA2 (802.11i) and TKIP support into VxWorks. Maintained both broadcom and atheros drivers. 802.1X Port based network access control; supplicant and authenticator support. EAPoL protocol analysis and debugging with wireshark to solve interoperability issues with various RADIUS servers. Wireless wireshark debugging of 802.11i fourway handshake.

Designed and implemented a multi-platform control API to support IDT's next generation packet processors. Required to architect a logical abstraction concept to hide underlying device details.Member of development team to implement an IDS (Intrusion Detection System, Snort) on an IDT Content Inspection Processor. Involved a detailed investigation of attack signatures and complex protocol analysis.Designed and developed simulation model of a PAX.port 4000 Classification Processor in C++ for integration with Intel’s IXP2400/2800 Network Processor Simulation Environment (Intel Workbench)Design and Implementation of Graphing and Metrics system to monitor software performance (written in perl script)Maintained BSP for PAX.ware 2500 evaluation systemPAX.port 2500 ASIC validationAnalysis of performance characteristics for packet classification algorithmsAutomation of software packaging system (Perl script)Coded and fixed various features for the IDT PAX.works SDKContributed in the hiring process for new verification engineers. Conducted interviews with multiple candidates

Member of the Network Processor team on the Terabit Interceptor project - A next generation packet-optical core switchDesign and implementation of a queuing / forwarding system for an Intel IXP1200 Network Processor to interface with a host CPU and Multiple MAC devices within a Gigabit Ethernet switch / IP router. Involved design with 6 parallel packet processing engines in a system with strict real-time constraints.Designed a dynamic scheduling algorithm to handle the tasks of buffering / forwarding in a congested systemDesigned the transmit scheduling system to send en-queued packets on the linkDesign interface to host CPU via Strong ARM processor on board the Intel IXP1200Worked with Intel to understand the IXP1200 architecture and reference designWorking with other team members to establish system wide interface specificationFiled a patent as a result of this workMember of design team to implement ATM capabilities (ATM over SONET) on the OPTera Metro 3000 product lineDesign and implementation specifics of circuit pack diagnostic functionality. Involved ATM cell generation to verify interfaces between ASICS throughout the circuit pack.Design and implementation of a fault protection mechanism for the circuit pack. Involved inter-processor communication to achieve < 60 ms equipment protection switching time.System integration testing of ATM functionality for the OPTera Metro 3000 product line

B Sc., Computer Science

B. Esc., Electrical Engineering

B. Sc., Computer Science