David Bauerle Email and Phone Number

Designed a new sensor interface board to improve noise performance and implement a FPGA digital processor:o Designed a new analog front end that consisted of the following: - Photodiode and LED - Trans-impedance amplifier (TIA) - Differential analog variable gain - Multichannel Analog to digital conversion, 4 channel, 16 bit SAR, 480ksps o Architected and wrote Verilog code consisting of: - Xilinx Spartan-6 XC6SLX75 - Several FIR filters - Complex math functions - Device and processor interfaceso PCB Layout and testing - Completed 8 layer PCB layout in Altium - Completed board bring up and testing

Smart Start designs and manufactures vehicle interlock systems for drunk driving.• Fixed the existing new camera design that was not functioning properly:• Redesigned existing switching power that was causing noise on the automobile radio.• Completed design reviews of all existing hardware designs and recommended improvements.

Completed the circuit design of the main circuit board for a Carrier Ethernet Interface box including:o Cavium Processor, Quad Core, 600 MHzo DDR2 SDRAM, 8x 64Mb x16, 333MHz, SSTL18o USB buso Altera Stratix GX FPGAo PCI Express bus, 2.5 Gbso Four XAUI 3.25 Gbs interfaceso RLDRAM, 2 x 16Mb x 36, 500 MHz, SSTL18o QDR II, 1Mb x 36, 200 MHz, SSTL18o Maxim DPLL precision clock generationo Verilog code for 3 Lattice CPLD’s

Designed an HD Digital Video Recorder:o Marvell ARM-9 RISC dual core 1 GHz processoro PCI Express buso Three Gigabit Ethernet portso DIMM 400Mhz DDR memory moduleManaged, designed, integrated, and tested a HD 360 degree multi-sensor camera.o 10 GB optical XAUI interfaceo Eight Sony 5 Megapixel sensorso Altera Stratix GX FPGAo Verilog video processing and XAUI interface codeo Multiple PCB designso Freescale 8 bit processor C programmingo Custom OpticsManaged, designed, integrated, and tested a 4 channel Mobile Digital Video Recorder for police and bus applications.o Altera Cyclone FPGAo Verilog video processing codeo 8 bit processor C code accelerometer monitoringo Board PCB design with X-scale RISC Processor

Led a small team of engineers developing Optical SONET and data communications test equipment.Designed, integrated and tested a next generation platform for an OC-48 and OC-192 deep channel BERT tester that helped win a major contract. This project required several design disciplines:o Large high-speed (155 MHz) clock switching matrixo High-speed (3.125 Gbs) XAUI backplane serial interface. 16 Bi-directional channelso Several high speed PLL designs (155 MHz and 622 MHz)o Large Altera S80 FPGADesigned, integrated, and tested a dual channel Optical Gigabit Ethernet test platform.o SFP optical interface (1.25 Gbs)o Marvell PHYo High speed memory interfaceDesigned, integrated, and tested an OC-192 (10 Gbs) electrical interface test platform, which generated in excess of $1.5 million in revenue.o 622 MHz PLL designo 622 MHz by 16 bit parallel PECL interface

Responsible for the development of security products. Led many project teams that developed mainly video products using analog and digital processing. Responsible for major technical decisions within the engineering group.Developed, maintained, and monitored a $6.0 Million budget.Led the development team for a new proprietary serial protocol (UUSP). Performed system level design and led the development of a new access control security system using a PowerPC processor.