David Bond Email & Phone Number

Ottawa, Ontario, Canada

Provided technical leadership for Architecture, Design, Verification, and Modeling teams through two significant and simultaneous events: the Covid-19 pandemic and the deteriorating relationship between the US Government and China – specifically with Huawei. As a technical leader supervised three distinct teams:1. The network processor team as it pivoted from being a chip and sub-system team to an IP delivery team and finally to an ‘N+2’ future research team. Defined the vision for the team, negotiated project parameters with HQ, managed & motivated the team, and guided the organization through two successful N+2 projects and the launch of a third. The completed projects provided significant reductions silicon area and power while dramatically increasing performance, within the constraints imposed on Huawei2. The Canadian staff of Huawei’s ARM core architecture team which is responsible for major components of the “LITTLE”, power & area efficient core that is employed in multiple applications and product lines. Reformed a team of network processor architects to deliver a new type of processor with different constraints, project goals, and methodologies. The team successfully produced architectural improvements and documentation for four processor cores, each with unique challenges and requirement goals3. The Edge Forwarding Processor team which was organized to perform research on emerging technologies related to the Data Center and Edge Computing

Ottawa, Ontario, Canada

Responsible for the architecture of the packet processing component of the network processor of Huawei's flagship core router and switch products:- Invented a new processor architecture and created a proof-of-concept demonstrating the improved performance while remaining within the area bounds of the silicon foundry. This major work required overseeing and facilitating the collaboration of the architecture, design, verification, microcode, and compiler teams - Authored the functional, architectural, and register specifications for a new network processor based on the newly invented architecture. Beyond completing the architecture of the processor, innovations were also pioneered in: the coprocessor subsystem to further reduce the silicon footprint of the processing sub-system; error handling; debug; and software updates

Responsible for the architectural deliveries of major components of a network processor: - Performance analysis and sizing of processing components to meet product requirements- A parameterized Network-on-Chip IP which was used in multiple blocks and continues to be used in many subsequent generations and derivative processors- A Local Memory controller which provided near-memory computation and RMW functions- An Instruction Memory controller for code delivery to the many core, many threaded processors- Area estimates; functional, architectural, and register specifications for each block- Peer review of many other blocks within the network processor

Ottawa, Canada Area

As an architect, responsibilities varied over the three phases of product development:1. Product Definition. Responsible for the generation of product ideas and the collection of requirements through customer visits & discussions, market analysis, product-area research, and feasibility & architectural investigations. These activities culminated in a detailed Product Description, a list of Design Requirements, a Specification (which included the architectural requirements and critical design notes), and a Users’ Manual2. Product Implementation. Responsible for answering technical questions regarding the requirements, specifications, standards, and IP integration. Responsible for ensuring that the Design and Verification teams implemented the intended functionality3. Product Validation. Supporting the lead customer to ensure the product is used correctly and successfully turns‐on in their product.Served as the architect on a variety of product developments: Power PC host bridges; Rapid IO endpoint IP; laser printer SOC; PCI Express interconnect for servers (investigation); and Rapid IO switch.

Ottawa, Canada Area

Scheduler architect for an optical cross bar capable of supporting up to 128 OC192‐rate packet andTDM connections with multiple priorities:- Schedule Algorithm development suitable for partitioning and implementation in FPGAs- Authored the functional specification of the scheduler algorithm- Implemented the design and guided verification team to successfully deliver the scheduler- Collaborated with the hardware design group to optimize FPGA partitioning and to automate validation consistency between the PCB and FPGA designs- Debugged multi‐switch systems for customer demonstrations

Ottawa, Canada Area

Architect and Chip-Prime for an OC3/OC12 framer‐mapper:- Led a design and verification team to convert the T1/T3 framer‐mapper into IP and integrate it with the additional SONET logic to produce a full OC3 framer-mapper- Spearheaded T1/T3 Framer‐mapper RTL verification:- Primed the gate‐simulation of the device and introduced new methods which found timing and logic errors in the design- Modeled & verified the jitter generation and attenuation of the clock recovery logic- Led the lab debug of the context switched time distribution PLL and invented a method to allow simulation to cover the extended time periods required to expose the anomaly observed in the lab

Waterloo, Canada Area

Accomplishments included:- Architectural definition and RTL implementation of a chip-set which doubled the performance of the previous X-terminal product- Developed methodologies for documenting, developing, and verifying RTL-based designs- Headed a team to architect one of HP’s first digital cameras- Oversaw an integrated team of ASIC, RF, and Industrial designers for an early WiFi product

Duties included:- Architecture and Design of DRAM/VRAM controller for second generation X-terminal- Benchmarking and analysis plus innovative architecture increased performance 10-fold- RFI and EMC testing of X-terminal devices

Waterloo, Ontario, Canada

Collaborated on products including switching power supplies, ruggedized equipment:- Building, debugging, validating, discrete prototypes- Automating testing & validation procedures to provide efficient and repeatable results- Developing, debugging, and demonstrating embedded real-time software

M.A.Sc, Electrical Engineering

Supervisor: Prof. Seviora Thesis "A Standard Cell Implementation of a RISC for AI" was on the development of a RISC processor.

B.A.Sc, Electrical Engineering; Computer Science Option

Education record