David Bond Email & Phone Number

Ottawa, Ontario, Canada

Provided technical leadership for Architecture, Design, Verification, and Modeling teams through two significant and simultaneous events: the Covid-19 pandemic and the deteriorating relationship between the US Government and China – specifically with Huawei. As a technical leader supervised three distinct teams:1. The network processor team as it pivoted.

Ottawa, Ontario, Canada

Responsible for the architecture of the packet processing component of the network processor of Huawei's flagship core router and switch products:- Invented a new processor architecture and created a proof-of-concept demonstrating the improved performance while remaining within the area bounds of the silicon foundry. This major work required overseeing and.

Responsible for the architectural deliveries of major components of a network processor: - Performance analysis and sizing of processing components to meet product requirements- A parameterized Network-on-Chip IP which was used in multiple blocks and continues to be used in many subsequent generations and derivative processors- A Local Memory controller.

Ottawa, Canada Area

As an architect, responsibilities varied over the three phases of product development:1. Product Definition. Responsible for the generation of product ideas and the collection of requirements through customer visits & discussions, market analysis, product-area research, and feasibility & architectural investigations. These activities culminated in a.

Ottawa, Canada Area

Scheduler architect for an optical cross bar capable of supporting up to 128 OC192‐rate packet andTDM connections with multiple priorities:- Schedule Algorithm development suitable for partitioning and implementation in FPGAs- Authored the functional specification of the scheduler algorithm- Implemented the design and guided verification team to.

Ottawa, Canada Area

Architect and Chip-Prime for an OC3/OC12 framer‐mapper:- Led a design and verification team to convert the T1/T3 framer‐mapper into IP and integrate it with the additional SONET logic to produce a full OC3 framer-mapper- Spearheaded T1/T3 Framer‐mapper RTL verification:- Primed the gate‐simulation of the device and introduced new methods which found timing.

Waterloo, Canada Area

Accomplishments included:- Architectural definition and RTL implementation of a chip-set which doubled the performance of the previous X-terminal product- Developed methodologies for documenting, developing, and verifying RTL-based designs- Headed a team to architect one of HP’s first digital cameras- Oversaw an integrated team of ASIC, RF, and Industrial.

Duties included:- Architecture and Design of DRAM/VRAM controller for second generation X-terminal- Benchmarking and analysis plus innovative architecture increased performance 10-fold- RFI and EMC testing of X-terminal devices

Waterloo, Ontario, Canada

Collaborated on products including switching power supplies, ruggedized equipment:- Building, debugging, validating, discrete prototypes- Automating testing & validation procedures to provide efficient and repeatable results- Developing, debugging, and demonstrating embedded real-time software

M.A.Sc, Electrical Engineering

Supervisor: Prof. Seviora Thesis "A Standard Cell Implementation of a RISC for AI" was on the development of a RISC processor to.

B.A.Sc, Electrical Engineering; Computer Science Option

Education record