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Primary expertise in semiconductor process integration, process engineering and patents, but also hands-on contributor to device, yield, waste reduction, and quality control. Demonstrates strong project management and team leadership. Works across different business groups to solve problems. Awarded 30 US patents.
Wheatstone Ip Law Corporation
View- Website:
- wsiplaw.com
- Employees:
- 5
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Principal Ip Technologist, Memory And Processor DevicesWheatstone Ip Law CorporationPittsburgh, Pa, Us
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Principal Ip Technologist, Memory & Processor DevicesWheatstone Ip Law Corporation Jul 2022 - Present
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Patent AnalystSemipat Consulting Mar 2021 - PresentUnited StatesOver 25 years of experience in the semiconductor industry and granted 30 US patents. Services include invention disclosure review, patent technical review, evidence of use evaluation, and claim charts.
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Principal Semiconductor Manufacturing Process EngineerKromek Group Plc Jan 2020 - Jan 2021Zelienople, Pennsylvania, Usa -
Principal Member Of Technical Staff: Feol Product IntegrationGlobalfoundries Jan 2017 - Nov 2018Fab 8, Malta, Ny• Chaired the Development Change Review Board for 7nm FEOL and improved documentation, review effectiveness, and tracking.• Coupled the change review process to implementation systems to decrease implementation time by over 50% and improve first-time-right metrics.• Served as technical chair for FinFET Patent Committee: Performed prior art searches, drafted and evaluated claims, and dispositioned invention disclosures. • Owned several "special" projects, especially those requiring multi-disciplinary teams to solve challenging, high impact, problems. -
Principal Member Of Technical Staff: Feol Process IntegrationGlobalfoundries Jan 2014 - Dec 2016Fab 8, Malta, Ny• Led team of FEOL integration, process, device, and TCAD engineers to develop STI, Wells, and Fin Reveal segments of 7nm FinFET technology. • Refined SPC methodologies and measurement sampling protocols for Fab 8. • Improved yield and manufacturability for 32 nm SOI-EDRAM technology (Oban APU for Xbox).
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Globalfoundries At Albany Nanotech: Feol Exploratory ResearchGlobalfoundries Aug 2013 - Dec 2013Albany, New York, Usa• Developed and patented a high mobility channel architecture for CMOS.
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Globalfoundries Assignee To Imec: Front End Exploratory ResearchGlobalfoundries Aug 2011 - Jul 2013Imec, Leuven, Belgium• Advocated for company interests and contributed to IMEC Ge and SiGe channel programs• Initiated and chaired Front End Exploratory Research Team for shared learning and tech transfer among company researchers in Belgium, New York, and California• Systematically evaluated dielectrics to develop the MIMCAP stack used in GlobalFoundries 14nm technology. Worked closely with colleagues in Germany, Belgium, New York, and California.
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Staff Front End Integration Engineer: 32 And 22 Nm ProgramsIntel Aug 2008 - Aug 2011Fab D1D, Hillsboro, Oregon, Usa• Owned 22 nm Fin and STI for D1D Ramp Integration. In 8 months, reduced fin width and height variability by over 30% and defects by 20 die per wafer. • Owned integration for Si starts, STI, Wells, and Poly modules for Intel 32 nm logic technology. Ramped to HVM, improved yields and performance, and reduced costs. -
Intel Assignee To Imec Core Partner Program: Logic And Flash MemoryIntel Jul 2004 - Jul 2008Imec, Leuven, Belgium• Chaired IMEC High-Quality / High-k Team. Improved HfO2 quality with optimization of ALD growth conditions. Reduced EOT growth through degas optimization.• Drove performance and yield improvements for IMEC Germanium program.• Investigated high k dielectrics for floating gate and nitride flash memories.
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Process Engineer: Rtp / Diffusion GroupIntel Oct 1995 - Jun 2004Fab D2, Santa Clara, California, Usa• Led tool selection team and process implementation for radical oxidation process used for STI Liner Oxidation and Tunnel Oxide on 90 nm Flash products.• Owned RTP process on logic and flash technologies and drove improvements to product performance and yield, process control, runrate, manufacturability, and cost.• Key Intel Awards: NiSi Development for Performance Enhancement, RTA TSOX Process Development, STI Liner Tool Selection and Process Development, Microprocessor Performance Enhancement, Enabling of Pentium III 600 MHz Introduction, RTP Reuse Team, RTA Runrate Improvement.• Team Chair: Flash High-k Working Group, Selective Epitaxial Growth Tool Selection, RTA Availability Improvement Team, NiSi Focus Team, RTA Joint Engineering Team.
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Post-Doctoral Researcher: Plasma DopingVarian Semiconductor Feb 1995 - Sep 1995Palo Alto, California, Usa• Characterized, improved uniformity and reduced contamination for Plasma Doping (PLAD) process.• Converted alpha tool from 150 to 200-mm wafer processing. Supported customer demos.
David Brunco Skills
David Brunco Education Details
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Gpa 3.9/4.0 -
Gpa 4.9/5.0
Frequently Asked Questions about David Brunco
What company does David Brunco work for?
David Brunco works for Wheatstone Ip Law Corporation
What is David Brunco's role at the current company?
David Brunco's current role is Principal IP Technologist, Memory and Processor Devices.
What is David Brunco's email address?
David Brunco's email address is db****@****mit.edu
What is David Brunco's direct phone number?
David Brunco's direct phone number is +140896*****
What schools did David Brunco attend?
David Brunco attended Cornell University, Massachusetts Institute Of Technology.
What are some of David Brunco's interests?
David Brunco has interest in Gardening, Traveling, History And Current Events, Education, Hiking, Science And Technology, Bicycling (And Bicycle Repair), Cross Country Skiing, Disaster And Humanitarian Relief, Human Rights.
What skills is David Brunco known for?
David Brunco has skills like Nanotechnology, Spc, Ic, R&d, Physics, Reliability, Jmp, Rtp, Process Integration, Sige, Germanium, Iii V.
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