David Brunco Email & Phone Number

Pittsburgh, Pa, Us

United States

Over 25 years of experience in the semiconductor industry and granted 30 US patents. Services include invention disclosure review, patent technical review, evidence of use evaluation, and claim charts.

Zelienople, Pennsylvania, Usa

Fab 8, Malta, Ny

• Chaired the Development Change Review Board for 7nm FEOL and improved documentation, review effectiveness, and tracking.• Coupled the change review process to implementation systems to decrease implementation time by over 50% and improve first-time-right metrics.• Served as technical chair for FinFET Patent Committee: Performed prior art searches, drafted and evaluated claims, and dispositioned invention disclosures. • Owned several "special" projects, especially those requiring multi-disciplinary teams to solve challenging, high impact, problems.

Fab 8, Malta, Ny

• Led team of FEOL integration, process, device, and TCAD engineers to develop STI, Wells, and Fin Reveal segments of 7nm FinFET technology. • Refined SPC methodologies and measurement sampling protocols for Fab 8. • Improved yield and manufacturability for 32 nm SOI-EDRAM technology (Oban APU for Xbox).

Albany, New York, Usa

• Developed and patented a high mobility channel architecture for CMOS.

Imec, Leuven, Belgium

• Advocated for company interests and contributed to IMEC Ge and SiGe channel programs• Initiated and chaired Front End Exploratory Research Team for shared learning and tech transfer among company researchers in Belgium, New York, and California• Systematically evaluated dielectrics to develop the MIMCAP stack used in GlobalFoundries 14nm technology. Worked closely with colleagues in Germany, Belgium, New York, and California.

Fab D1D, Hillsboro, Oregon, Usa

• Owned 22 nm Fin and STI for D1D Ramp Integration. In 8 months, reduced fin width and height variability by over 30% and defects by 20 die per wafer. • Owned integration for Si starts, STI, Wells, and Poly modules for Intel 32 nm logic technology. Ramped to HVM, improved yields and performance, and reduced costs.

Imec, Leuven, Belgium

• Chaired IMEC High-Quality / High-k Team. Improved HfO2 quality with optimization of ALD growth conditions. Reduced EOT growth through degas optimization.• Drove performance and yield improvements for IMEC Germanium program.• Investigated high k dielectrics for floating gate and nitride flash memories.

Fab D2, Santa Clara, California, Usa

• Led tool selection team and process implementation for radical oxidation process used for STI Liner Oxidation and Tunnel Oxide on 90 nm Flash products.• Owned RTP process on logic and flash technologies and drove improvements to product performance and yield, process control, runrate, manufacturability, and cost.• Key Intel Awards: NiSi Development for Performance Enhancement, RTA TSOX Process Development, STI Liner Tool Selection and Process Development, Microprocessor Performance Enhancement, Enabling of Pentium III 600 MHz Introduction, RTP Reuse Team, RTA Runrate Improvement.• Team Chair: Flash High-k Working Group, Selective Epitaxial Growth Tool Selection, RTA Availability Improvement Team, NiSi Focus Team, RTA Joint Engineering Team.

Palo Alto, California, Usa

• Characterized, improved uniformity and reduced contamination for Plasma Doping (PLAD) process.• Converted alpha tool from 150 to 200-mm wafer processing. Supported customer demos.

Phd, Materials Science And Engineering, Gpa 3.9/4.0

Activities and Societies: Alpha Phi Omega.Advisor: Prof. M O Thompson. Minor: Physics. • Studied laser processing of heteroepitaxial SiGe.

B.S., Materials Science And Engineering, Gpa 4.9/5.0

Concentration: Electronic Materials