David Cornfield Email & Phone Number

411 Legget Dr, Kanata, ON K2K 3C9

I developed adaptive filtering algorithms needed for the next generation of high bandwidth signal integrity products.

415 Legget Dr, Kanata, ON K2K 3R1

I created MemoryModel, a tool that compiles Firmware source code into a hierarchy of Python objects that enable interactive inspection of embedded RAM through a model of Firmware data structures.

Ottawa, Canada Area

I developed a register definition tool called Spacecraft that is focused on an API accessible, memory resident model rather than input and output formats; it is the culmination of years of experience manipulating the hardware/software interface for various audiences.

423 Bronson Ave., Ottawa, ON K1R 6J5

I partnered with Sleepwell Property Management to design, develop, deploy and ultimately market Quartermaster, a multi-platform software application that facilitates the operational aspects of property management while providing transparency for clientele.

1 Hines Road, Suite 204, Kanata, ON, K2K 3C7

In this position I led the technical aspects of the Verification Program of the Transport Division which primarily consisted of identifying, implementing, deploying and supporting solutions to recurring Design & Verification problems. These problems ranged from purely technical issues (test bench & verification IP architectures, regression suite.

1 Hines Road, Suite 204, Kanata, ON, K2K 3C7

As Principal I primed the technical Verification effort for numerous projects, which included implementing and maintaining top level test benches, architecting and integrating verification IP, providing baseline test cases for others to expand upon, as well as managing build, compile & regression tool flows.I also designed and maintained hardware in a.

Kanata (Various Sites)

I was the designer & custodian for C models of various telecom protocols: SONET, OTN (GFEC/EFEC), 10GBASE-R, 10GBASE-X, SFI-4.2/5, POS, ATM, GFP, etc.I also did lots of RTL Design and Verification over the years, including one project where I automated the generation of 4400 self-checking datapath tests, which set me on the course of verification lead.

115 Rue Champlain Gatineau, QC J8X 3R1

PCB Design, FPGA Design & Lab work.