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Mentored an inexperienced team of digital design and verification engineers to develop ultra high-speed telecommunications platforms that are beating the competition and deployed with international carriers.Led 3 Telecommunications and SOC ASIC developments to rev A production release.25 years experience in digital and mixed-signal product development - including all aspects of FPGA and VLSI chip development and product management.Specialties: VHDL & Verilog (coding, verification, synthesis, timing closure),Communications protocols (OTN, SONET, Ethernet, ATM, T1/E1/T3/E3, I2C, SPI, PCIe, ...)Media protocols (ST2022, ST2110, SDI, AES3, AES67)MIPS, ARM & Nios II MicroprocessorsSoftware (C, C++, Ada, Perl, Tcl, HTML, Java, ...)
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Digital Ic Design ManagerMaxlinear Mar 2022 - PresentCarlsbad, California, UsNext generation DSP architecture; manage/mentor team of junior engineers to complete device validation and characterization and to design 802.3 subsystem of next gen DSP. -
Sr Principal Asic Design EngineerMaxlinear Jun 2020 - Jun 2022Carlsbad, California, UsFPGA emulation of high speed DSP ASIC; Functional validation of silicon prototype; Design and verification of cross-chip data-path.
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Principal Engineer - R&DGigaio Mar 2020 - Apr 2020Carlsbad, California, UsDesign and implement FPGA for next generation PCIe networking products.Assist hardware team with development and debug of current products. -
Principal Design EngineerMacnica Americas Feb 2013 - Feb 2020Solana Beach, Ca, UsFPGA implementation of cutting edge Video Processing IP for product development, All digital clock recovery, Xilinx & Altera FPGA integration. -
Principal Engineer - SocIpg Photonics Jan 2011 - Feb 2013Oxford, Ma, Us- Leader and technical go-to person for FPGA based implementation of 10Gbps and 100Gbps optical telecom platforms.- Develop and maintain proprietary Communications IP including OTN, SONET/SDH and GFP processors. -
Principal EngineerMultilane Oct 2008 - Jan 2011Houmal, Mount Lebanon, Lb- Mentor and lead teams of junior digital engineers in the implementation and verification of FPGA based 10Gbps optical network access projects. Our team was spun off after product success to start the Beirut office of IPG Photonics.- Design services contractor: (ASIC Timing Closure, CAD Infrastructure support) -
Product EngineerPmc-Sierra Mar 2008 - Aug 2008Us- For this contract position, I was responsible for characterizing new analog IP in a 45nm test chip. - This position involved designing, implementing and executing tests of analog and digital IP circuits on the lab bench and an HP83000 IC Tester. -
Leader - Product DevelopmentPmc-Sierra Sep 1995 - Mar 2007Us- Responsible for the complete development cycle of 4 communications and SOC chips (three of which were released to production without any design revisions required).- Effectively led teams of 3-20 people across multiple sites and all discipines of ASIC design to accomplish development goals.- In addition to these main tasks, I researched future product directions and assisted wherever another design team needed my help.
David Culley Skills
David Culley Education Details
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Simon Fraser UniversityCommunications -
Simon Fraser UniversityElectronics Engineering
Frequently Asked Questions about David Culley
What company does David Culley work for?
David Culley works for Maxlinear
What is David Culley's role at the current company?
David Culley's current role is Digital IC Design Manager at MaxLinear.
What is David Culley's email address?
David Culley's email address is cu****@****eee.org
What is David Culley's direct phone number?
David Culley's direct phone number is +185825*****
What schools did David Culley attend?
David Culley attended Simon Fraser University, Simon Fraser University.
What skills is David Culley known for?
David Culley has skills like Asic, Verilog, Fpga, Soc, Vhdl, Integrated Circuit Design, Ic, Tcl, Ethernet, System Architecture, Embedded Systems, Product Development.
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