Utilizing deep technical experience combined with a commercial and business mindset, I provide NED/advisory and consultancy on complex software/hardware systems to startups and high-technology businesses.Past assignments include 18 months at a Quantum security startup assisting CEO/CTO and Chief Scientist creating roadmaps, plans, budgets and system architecture/IP, with hands on work developing product platform and fully working prototypes.

Revised strategic and engineering approach for technology within the business. Produced departmental business plan, budget and roadmap for proprietary solutions. Setup and led collaboration with Intel to develop architecture and reference design for immersion cooled enterprise scale BTC miners using next generation Intel Blockscale ASICs.Market conditions in the Cryptocurrency market forced reorganization and closure of business units, followed by adminstration and sale of deployed assets.

I founded SOMNIUM Technologies to exploit interest from silicon vendors in better development tools – exploiting deep understanding of software and hardware interactions to build software products to save engineers time, money and generate the best possible technical results. Devised a business plan, raised equity investment and recruited the other founders and employees. Maintained the financial model, obtained R&D grants, and held monthly board meetings with investors.Identified opportunities and negotiated contracts for product development and design services with multiple tier-1 silicon vendors. We displaced RedHat as a GNU maintainers for a major silicon vendor project, and developed products used by over 100,000 engineers, reaching the highest level of tools supplier status with our silicon partners.Devised “resequencing optimisation” techniques to optimise code for a microprocessor and its specific memory system, resulting in multiple patent filings and grants. Benchmarks validated our claims that DRT generated considerable technical benefits versus other tools, typically yielding 10..30% smaller code, 20..50% higher performance and up to 50% lower energy consumption.Recruited and man managed the engineering and customer support teams. Though mostly “hands off” as a developer, I had significant input to SOMNIUM’s internal engineering and customer support activities including overall strategy, technical brainstorming sessions, release reviews and post-mortems.Authored marketing materials and attended international conferences , making over 10 technical presentations with our tier-1 silicon partners and culminating in DRT being 1 of 3 finalists in ARM TechCon 2016’s most innovative software product. Setup and managed relationships with 8 international resellers (including Mouser) and helped manage website integration between resellers and our e-commerce store. Setup partnerships with ARM, EEMBC and other leading software vendors.

Evolving the architectural/microarchitecture of the DXP processor system.Development of new software and hardware technologies for multi-core, multi-threaded software development, debugging and optimization.Close co-working with management and engineering staff involved in silicon implementation and verification, platform & board design, and modem implementation.

2nd non-founding i.e. 6th employee (3rd non millionaire ;-)Member of the Baseband Silicon Management team – involved in coordination and management of the baseband silicon team’s activities.Architectural definition of the DXP instruction set, mechanisms to support RTOS and debugging tools, and contributed to the overall SoC architecture and verification flow.Recruited a world-class SDK team, and helped recruit several other key members of the silicon and modem teams.Management and technical leadership of the SDK team, producing acommercially and technically successful world-class multi-core development environment, used internally for silicon design/verification and modem development, and also by a large number of external customers.Development of new software and hardware technologies for multi-core, multi-threaded software development, debugging and optimization.Close co-working with management and engineering staff involved in silicon implementation and verification, platform & board design, and modem implementation.Filed patents on hardware/software infrastructure for power management, linker-based cache optimization, and NAND boot mechanisms.

Architectural definition of features to support RTOS, and debugging/profiling tools.Implemented software models of debug architecture and NEXUS APIs to access debug & profiling hardware.Implemented C/System C interface to RTL simulation of OneDSP systems and connections to hardware emulation of RTL.Implemented low-level verification and bringup tests for test silicon.Performed bringup of prototype silicon devices.Optimized key software components (audio codecs, benchmark test suites) for potential customers.Visited potential customers to provide technical training and information on the OneDSP architecture & software tools.Assisted with due diligence activities for two potential acquirers.Filed & granted several patents for CPU system architecture, debug & profiling hardware.

Involved in multi-core implementation of TCP/IP stack.Design & implementation of target interface software.Design, formal specification & implementation of multi-core debug agents for Transputer networks (allowing debugging of systems with up to 8192 processors).Architectural definition of RTOS support and debug hardware for Chameleon and SH-5 processors.Management and Technical leadership of Debug Software Tools Team for Chameleon (split between UK and Italy), SH4 and SH5 processors (split between UK, Japan and US).Technical lead of IEEE 5001 Nexus Debug Architecture Software API activities – proposed and agreed technical aspects of NEXUS hardware and software interface with major industrial bodies (Motorola, Infineon, Hitachi and STMicroelectronics).Worked between UK & San Jose on collorative development of the SH5 architecture and software tools.Directed verification of key parts of Chameleon & SH5 CPU and debug systems.Initial bringup of Chameleon & SH5 on hardware emulation and silicon devices.Patents granted on real-time non-intrusive debug and profiling mechanisms, architecture for RTOS support, and related systems/software.