SERDES DFE Receiver Design

Senior Analog Circuit Design Engineer With High Speed Serial TeamDesigned analog sampling summer with DFE tap charge injection, DFE tap biasing, and calibration circuitry for a 15–tap DFE in a 32Gb transceiver using 32nm SOI CMOS.Pioneered automated calibration and measurement techniques for complex simulations enhancing productivity during the design and verification process. Created several Verilog-A modules to automate measuring transceiver characteristics, such as: sensitivity, offset, summer linearity, Amin, latch setup and hold times, DFE tap accuracy, rotator linearity, and step response. These Verilog-A modules and simulation techniques were leveraged across multiple HSS design teams, substantially improving productivity of many designers.Responsible for the DFE design on a 1-tap 15Gb low-power transceiver in 32nm SOI CMOS. Collaborated with a global development team providing DFE specifications, description, and complete simulation results insuring a first pass success.Worked with multiple development teams migrating HSS receivers to the advancing CMOS technology while improving performance. CMOS Technology progression included: 90nm, 65nm, 45nm SOI, and 32nm SOI. My responsibilities focused on design and verification of key analog circuits in the receiver, such as: summers, isolation buffers, calibration circuits, clock distribution, peaking amps, signal detectors, and reference biasing.Designed a quadrature clocking circuit with a divide-by-3 option and a high speed clock gate.