David Garau work email
- Valid
- Valid
David Garau personal email
Over the course of over 20 years of industry experience I have acquired a deep and broad set of skills and abilities. These range from board level digital high-speed design to coding resource efficient FPGA designs to embedded Linux drivers and systems. This breadth of skills gives me the ability to not only come up with novel solutions to problems at a system architecture level but to also implement that architecture using the most appropriate technologies, be they hardware, FPGA or software.
-
Senior Fpga DeveloperDali Wireless Nov 2016 - PresentMenlo Park, California, UsAll aspects of CPRI payload data manipulation and routingDSP algorithm development, modeling and implementationBoard level system bring-up and debug -
Senior Fpga DeveloperDali Wireless Jan 2015 - May 2016Menlo Park, California, UsIntroduced an FPGA design flow which included:-introduction of a revision control system-scripted automated build system-AXI-LITE IP infrastructure for the modular definition of system control planes (configuration and status registers)Implemented standards compliant CPRI PHY layer block using the Xilinx GTX transceivers. The block is fully software configurable and can be configured to operate from CPRI line rates 1 to 8 through its register interface.
-
Engineering Manager - Silicon ValidationTeradici Corporation Apr 2005 - Jan 2015Palo Alto, California, UsAmongst the first employees at Teradici, I was primarily responsible for the FPGA prototyping, bring up, and validation of Teradici’s PCoIP SOC ASIC devices. During the early days as the company was growing I was also directly involved with customers and sales support, performing, applications and sales engineering and directly assisting with customer issue resolution. As the company grew further, I helped build up both the validation and applications engineering teams. -
System Design And Validation EngineerPmc-Sierra 1999 - 2005UsResponsible for the validation of prototype telecommunication ASICS. These are complex multi-million gate devices which implement complete PHY layer SONET and/or PDH functionality and have in excess of 1000 configuration registers. Protocols include SONET, PDH, ATM, and POS.Bus protocols include UTOPIA/POS levels 2&3, SBI and other proprietary signaling protocols. Validation includes many diverse stages all of which I have been directly responsible for on numerous projects:-Formulation of a Test Plans-Development of Hardware Test Platforms-FPGA Design and Coding-Software Test Environments-Execution of Feature Tests
David Garau Skills
David Garau Education Details
-
University Of VictoriaB.Eng. In Electrical Engineering -
British Columbia Institute Of TechnologyDiploma In Robotics And Automation Technology
Frequently Asked Questions about David Garau
What company does David Garau work for?
David Garau works for Dali Wireless
What is David Garau's role at the current company?
David Garau's current role is Senior FPGA Developer at Dali Wireless.
What is David Garau's email address?
David Garau's email address is dg****@****ici.com
What schools did David Garau attend?
David Garau attended University Of Victoria, British Columbia Institute Of Technology.
What skills is David Garau known for?
David Garau has skills like Debugging, Embedded Systems, Asic, Field Programmable Gate Arrays, System On A Chip, Fpga, Application Specific Integrated Circuits, Soc, Verilog, Semiconductors, Tcl, Vhdl.
Free Chrome Extension
Find emails, phones & company data instantly
Download 750 million emails and 100 million phone numbers
Access emails and phone numbers of over 750 million business users. Instantly download verified profiles using 20+ filters, including location, job title, company, function, and industry.
Start your free trial