Member of the Design For Test/Debug team.

Senior technical lead supporting multiple teams of engineers doing development and validation of enterprise SSD firmware, with a focus on customer feature development and product launch. Current responsibilities include architecture and design of new features, mentoring and development of technical staff, and assessment of features to support customer requirements and enable product launch.Previous roles as technical product lead and technical team lead included included several aspects of product and program management, customer interfacing, technical leadership, and team development. Technical focus areas include media policies, RTOS system development, multicore issues, development of robust and scalable firmware implementations, and facilities for firmware debug and characterization.

Design and development of Itanium processor firmware specializing in multi-core and multi-threading support and the containment, handling, and correction of errors at the processor and system BIOS levels. Extensive pre-silicon and post-silicon triage and debug experience on internal systems as well as multiple OEM partner hardware and BIOS platforms. Direct interfacing with multiple OEM partners and sustaining customer support for deployed Itanium platforms. Lead or contributed to numerous improvements in firmware robustness, scalability, and debug features resulting in increased product reliability and improved customer experiences.

Owned pre-silicon test plan development and execution for the x86 compatibility hardware on early Itanium processor.Helped design, develop, and support a highly automated, very high throughput, modular post-silicon test infrastructure. This included random test generation, execution, and extensive post-silicon triage and debug.Created new modules for extending existing focused tests and random generator content to provide coverage of multiprocessor functionality such as shared memory, semaphores and bus arbitration.Supported additional modules from validation partners for focused validation of specific CPU features.

Developed design and micro-architectural validation plans covering bus compatibility and correctness for the 82450nx x86 server chipset.Developed infrastructure modules to provide bus functional models for PCI and cpu bus agents and enable broader system level testing of x86 server chipsets. Early checker coverage was enabled and both functional and performance enhancements incorporated as required.Worked with designers and post-silicon lab teams to create a new infrastructure which captured silicon state from failed post-silicon tests and imported the data into pre-silicon RTL models for failure reproduction and debug (RTL replay).

Worked and mentored with the Design Automation Group. Developed scripts and CAD tools to implement and improve on several design flows, automatically scale Cadence schematic databases, and perform hierarchal analysis of designs.

Held positions as summer/winter intern. Focus included hardware and software validation on digital cross-connect systems in the Titan series, including the 5300, 5300L and 5500. Significantly enhanced the system Database editor (DBE) for upgradability and use by in-field technicians, added customer features, and added reliability/recovery support.