David Kauer Email & Phone Number

Armonk, New York, NY, US

I design logic for Power Server Systems, been involved in verification roles, and actively engaged in a patent group. This entails designing high-level architecture, writing & debugging VHDL code, developing C/C++ based drivers & checkers, and introducing new and creative ideas to IP Law.I work with logic, verification, and physical design teams around the.

Supervising multiple labs and guiding students on ASIC design and verification techniques. This entails simulation, synthesis, and layout tools such as Modelsim, Synopsys Design Compiler, and Cadence Encounter/Virtuoso. Students also learn the elements, semantics, and design styles for HDLs (VHDL/Verilog), combinational and sequential circuits for.

I was responsible for converting the class materials and HDL used for Purdue's ECE 337 ASIC Design course from VHDL to Verilog. Tasks include converting all VHDL source code to Verilog, simulating source and synthesized Verilog designs for all Lab materials, and modifying python-based grading scripts to evaluate Verilog designs. I'm also continuing an ASIC.

Acquired research and development experience on a System-on-Chip (SOC) Embedded Linux Platform. Consulted with Intel and Videon Central Staff on development issues and technical advice. Created 100-page setup and development pocket guide for Intel Media Processor SDK.

Researched and analyzed legislation utilizing Legislative Staff members and online resources. Engaged in collaborative teamwork to aid constituents, systematize congressional files, and compile schedule-related documents.

Bachelor Of Science, Electrical Engineering

High School Diploma