David Kohen

David Kohen Email and Phone Number

R&D Process Engineer│Semiconductor Industry @ Intel Corporation
(408) 765-8080
David Kohen's Location
Hillsboro, Oregon, United States, United States
About David Kohen

More than 12 year experience in semiconductor, specialized in the epitaxy of semiconductor materials, process and equipment technology. Solid background in device physics, metrology and integration. Technical Skills and Expertise: semiconductor epitaxy, chemical vapor deposition (CVD), metal organic chemical vapor phase epitaxy, III-V electronic devices, photovoltaics and solar cells, material characterization including structural and electrical/optical properties, DOE and statistical methods (JMP), Logic and memory process integration

David Kohen's Current Company Details
Intel Corporation

Intel Corporation

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R&D Process Engineer│Semiconductor Industry
(408) 765-8080
Website:
intel.com
Employees:
10
David Kohen Work Experience Details
  • Intel Corporation
    Research Engineer @ Component Research
    Intel Corporation Dec 2021 - Present
    Santa Clara, California, Us
    Next generation logic deviceQuantum computing
  • Intel Corporation
    Staff Process Engineer
    Intel Corporation Jan 2020 - Dec 2021
    Santa Clara, California, Us
    Pathfinding and technology development of Si Photonics and Intel Memory Technology (Optane) products.
  • Asm
    Senior Process Engineer - Product Development
    Asm Aug 2017 - Dec 2019
    Almere, Flevoland, Nl
    Epi Process Technology department- Process development of novel Epi layers for 5nm logic and beyond (GAA, nanowire nanosheet FinFET) and advanced memory technologies (VNAND, DRAM), including metrology development for such layers- EPI reactor product development, including tool matching procedures, repeatability and tunability optimization through hardware continuous improvement projects (CIP) - Technical interface with customers (major semiconductor manufacturers) for joint development projects (JDP) and technology development support and troubleshooting
  • Asm
    Senior Process Engineer - R&D
    Asm Nov 2015 - Aug 2017
    Almere, Flevoland, Nl
    ASM Corporate R&D department, located at the Imec research institute - Developed novel epitaxy and pre-clean processes for future technology nodes (10nm and beyond) with strong interactions with integration, device and metrology teams- Led Joint Development Program activities with Imec on advanced epitaxy layers for future logic and memory technologies- Contributed to cross-disciplinary projects on integration of novel materials and processes
  • Singapore-Mit Alliance For Research & Technology Centre
    Postdoctoral Researcher
    Singapore-Mit Alliance For Research & Technology Centre Oct 2012 - Oct 2015
    Singapore, Singapore, Sg
    - Optimized heteroepitaxial growth of III-V on Silicon, targeting low dislocation density- Conducted the epitaxial growth and optimization of of InGaAs HEMT on Silicon by MOCVD- Developed integrated wafer processes using Si CMOS and III-V devices- Responsible for troubleshooting and maintaining the MOCVD reactor in optimal working conditions
  • Massachusetts Institute Of Technology
    Visiting Researcher
    Massachusetts Institute Of Technology Nov 2012 - Jan 2013
    Cambridge, Ma, Us
  • Cea - Commissariat À L'Énergie Atomique Et Aux Énergies Alternatives
    Research Scientist, Phd Candidate
    Cea - Commissariat À L'Énergie Atomique Et Aux Énergies Alternatives Sep 2009 - Sep 2012
    Paris, France, Fr
    Silicon Nanowires for Photovoltaics:- CVD growth of silicon nanowire array with Al and Cu catalyst- Integration of silicon nanowire array with conformal radial junction into a working concept solar cellEarth-abundant dichalcogenide solar cells:- studied the secondary phases of CZTS material using Raman spectroscopytechnical skills acquired: CVD, UV and optical lithography, SEM, micro-Raman spectroscopy, XRD, TEM
  • Imec
    Junior Researcher, Intern
    Imec Oct 2008 - May 2009
    Leuven, Be
    Studied the passivation of GaAs and InGaAs interface with high-k oxides using MOS structures:- Interface trap density extraction by conductance method and CV measurements- Annealing experiments and their influence on interface trap densitiy
  • Tyndall National Institute
    Junior Researcher, Intern
    Tyndall National Institute Jun 2007 - Sep 2007
    Cork, Ie
    Investigated the chemical stability of lanthanum oxide using Fourier Transform Infrared FTIR spectroscopy

David Kohen Education Details

  • Grenoble Inp - Uga
    Grenoble Inp - Uga
    Nanoelectronics And Nanotechnology
  • Kth Royal Institute Of Technology
    Kth Royal Institute Of Technology
    Nanotechnology
  • Grenoble Inp - Phelma
    Grenoble Inp - Phelma
    Device Physics And Material Science

Frequently Asked Questions about David Kohen

What company does David Kohen work for?

David Kohen works for Intel Corporation

What is David Kohen's role at the current company?

David Kohen's current role is R&D Process Engineer│Semiconductor Industry.

What schools did David Kohen attend?

David Kohen attended Grenoble Inp - Uga, Kth Royal Institute Of Technology, Grenoble Inp - Phelma.

Who are David Kohen's colleagues?

David Kohen's colleagues are Daniel Ashton, Hector Vivanco, Alessandro Boza Vargas, Lean Teng Yew, Azzam Kamal, Noam Naveh, Khairul Akmal.

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