David Oates Email & Phone Number

Wilmington, Ma, Us

Since January 2021, I have focused on scoping SW architecture for new product development in parallel with the hardware design pre-tape out. I manage a team of 5 software technical leads each working on parallel software categories covering all aspects of a Linux based 5G ORAN O-RU (Radio Unit). Software planning, definition, development, and architecture tasks cover topics such as Embedded Secure Boot, ARM trusted FW, custom Secure Boot hardware, custom UBoot drivers, Linux kernel drivers, Linux User space driver and application development. The software developed includes custom RF transceiver performance algorithms such as Dynamic Pre-distortion (DPD), Closed Loop Gain Control (CLGC), VSWR, Zero IF Quadrature Error Corrections, real time Antenna Calibrations and JESD204 High Speed Serial link calibrations. With my application engineering background, I drive weekly meetings with software partners and customers to capture system level and software requirements for active products.

Wilmington, Ma, Us

Software Technical lead for API development of 4T4R and 8T8R cellular RF transceiver devices. I managed and mentored 5 local reporting software developers on a ~50 person software team spread across the US, Ireland, Europe, India and China. I was a technical lead on software architecture, and was responsible for day 1 hands on lab bring up of the transceivers and JESD204B/C high speed serial data interfaces (5Gbps to 32Gbps)• Managed Jira tickets for SW tasks• Led technical SW definition based on customer requirements• Enforced code style, SW quality, and SW test coverage• Responsible for day 1 silicon bring up of hardware + software

Wilmington, Ma, Us

C API driver development for tier 1 4G communications customersTransceiver Product Evaluation Software

Wilmington, Ma, Us

• Customer facing documentation• On site tier 1 customer support (Presentation skills)• Developed Customer Evaluation Software• Lab characterization of ADI wireless transceivers (3GPP/LTE modulated testing)• RF PCB schematic entry (Cadence Allegro), High Speed Digital layout experience• FPGA development (Verilog - Xilinx/Altera FPGAs), timing closure, encrypted Verilog models• JESD204B/C High Speed serial interface development (FPGA to ASIC)

Bachelor Of Engineering - Be, Electrical Engineering (Ee)

Bachelor Of Engineering - Be, Computer Engineering (Cpe)