20 yrs supporting IC design and process development for foundry, FAB and FAB-less customers.* On-chip ESD protection and Latch-up prevention, schemes/DRC/schematic/layout review. * device issues and limitations, debugging circuit malfunctions and production problems.* electrical characterization and modeling, DC, pulsed IV, RF and special measurements* relate physical product needs to factory device, process and PDK concerns.* Technical communications and presentations, Design Guidelines, Help ticket customer supportCapable with design tools, producing test chips, conducting laboratory experiments.* Cadence, Klayout, wafer probe station, GPIB instrument automation* DOE planning, analog and parametric data analysis CMOS, SiGe BiCMOS, extended voltage, SmartPower, TVS, Photodetector