David Roclin Email & Phone Number

Aix-En-Provence, Fr

Aix-En-Provence, Provence-Alpes-Côte D'Azur, France

Aix-En-Provence Area, France

XR5AXI - PCIe to AXI bridge - product ownerXLSOC - CXL to AXI bridge - product ownervDMA - Multi channel DMA - product ownerImprovement of the PCIe core - Gen3 Gen4 .Implementation of a generic PCIe switch, one ingress port to "n" egress port .FPGA hardware validation (Xilinx, Altera).Set up ASIC synthesis environment - DC ultra (Synopsys) and Oasys (Mentor).Set up script environment (dev, simu, synth) for Switch product (python).Contribute to Continuous Integration software (jenkins).Spyglass verification - Lint - CDC.customer support

Gif-Sur-Yvette

Title : "Integration of memory nano-devices in image sensors processing architecture"Titre : " Utilisation des nano-composants électroniques dans les architectures de traitement associées aux imageurs avec les technologies d'intégration 3D "My PhD project was centered around two objectives. First, to define a Spiking Neural Network architecture that could be implemented digitally in an ASIC. Second, to study the implementation of the SNN’s synapses with emerging nano-scale memories in order to exploit the high density level and the strong parallelism during a read or write operation when arranged as a crossbar structure.-Optimization and simulation of Spiking Neural Network using the STDP learning mechanism in order to allow its digital implementation (VHDL)-Low-level modeling of SNN and emerging memory nano-device (CBRAM) in VHDL-AMS-Low level studies of emerging memories in a crossbar topology (VHDL-AMS simulations - energy consumption - density of integration - Programming, reading mechanisms)-Design (transistor level) and test (packaged chip) of the 1st neuromorphic chip, co-integrating a 130 nm CMOS process with a CBRAM memory technologyTools and languages:Cadence, ModelSim, Xilinx suite, Virtex-4, PCB DesignSpark, VHDL, VHDL-AMS, Python, Perl, C++ Completed in december 2014

Fayetteville, Arkansas

- Layout of threshold gates of the MTNCL library for the MITLL Fully Depleted SOI (FDSOI) process Using Cadence tools-Master of Science thesis:"Optimum Transistor Sizing of MTNCL Threshold Gates for Various Design Constraints"For my Master thesis, I studied each threshold gate in the MTNCL library. For the transistors of each of these gates, my goal was to determine an optimum size, allowing the gate to have an optimum balance between energy consumption and gate delay. As a result, I showed that, on average, an increase of 60% in the energy dissipation in an optimized gate allowed the propagation delay to be four times faster than that of the minimum-sized counterpart. Using Cadence tools

Fayetteville, Arkansas

"Delay-Insensitive Cell Matrix" International Conference on Computer Design, July 2010

Master, Computer Engineering

Activities and Societies: Low Power CMOS Design, Delay-Insensitive Asynchronous Design, TTL, DTL, ECL, BiCMOS Design. VHDL, Verilog.

Master, Real Time Systems Architectures

Activities and Societies: Signal processing (theory), Advanced Digital Signal Processing, Multitasking systems and microprocessors, Signal.