Developing joint projects with semiconductor companies in Taiwan in the areas of DFT and Test Engineering. Initiating & directing R&D collaboration projects in number of design and test areas with selecting strategic customers and generating strategy for new business initiatives.

Founder of Electrical and Computer Engineering department. Developed, implemented and managed a complete B.S. degree program in Electrical and Computer Engineering from ground zero. Managed program budget, contents development, equipment, and tools evaluation in all areas.

• Managed multiple product design and test projects including schedule, milestones, and risk score cards with stake holders across multiple sites to ensure product delivery in time with optimized product cost.• Identified and drove the implementation of high impact DFT/test technology initiatives to enable massive test cost reduction and parallel testing.• Managed research and development of Design for Testability (DFT), manufacturability (DFM), debug (DFD) and reliability (DFR) for three-generation of intel products. • Developed test compression solutions for structural testing that decreases test time and volume by an order of magnitude. • Generated innovative DFT techniques to allow for the speed testing of circuits with multiple clock domains. • Developed and implemented DFT/DFX architecture, Published DFT/DFX design rules handbook. Implemented required DFT features based on technical specifications.• Developed and drove DFT/DFX methodologies and implementations in logic scan design, logic built-in self-test (LBIST), memory built-in self-test (MBIST), automatic test pattern generation (ATPG), and boundary scan (JTAG). • Performed structural test patterns generation and coverage analysis of deterministic and random test patterns to reduce the pattern count and still achieve test coverage goal and meet quality objectives. • Worked with physical and logical designers on DFT/DFX implementations to optimize silicon areas, power, timing and validated DFT/DFX features.

• Led cross-divisional teams including design, verification, ATPG, manufacturing, marketing to establish a top-down process flow and checklist to ensure meeting product quality and cost targets.Managed a team of 20-30 manufacturing test engineers including mentoring, performance review and appraisal. Led test engineers and designers in developing product test strategy based on product technical specifications. Led test engineering team executing test plan from product definition to tape-out and silicon bring-up. Managed test module developments and test equipment selection, qualification and procurement for CPU and chipset manufacturing. Optimized test process flow to reduce test cost and improve the quality of products. Determined the shopped product quality level for different customers based on analysis of test coverage, cycle time requirements and yield curves. Collaborated with designers to ensure product quality, test coverage, tester bring up and test pattern debug. Optimized the manufacturing processes including structural test, functional test, burn-in test, system test, and final test. Collaborated with colleagues across multiple sites to define strategy, plan, and product implementation. Made presentations as required, including at the executive level. Led efforts in eliminating functional tester requirements and saved millions of dollars of product cost.

• Strategic leader for HP-Compaq’s long-term design and test roadmap. Drove a top-down design and manufacturing strategy for part design, board level test and system level test integration.• Developed and implemented BIST, scan, and debug architecture for improving top-down test integration and system debug.• Developed and implemented an effective product roadmap in ICT, functional test, and system test. • Drove test equipment vendor selection and decision-making processes.

• Led microprocessor design-for-test architectures and strategies. • Project leader of high-speed CMOS communication chip design and test strategies. • Performed extensive analog and digital circuit simulation to analyze circuit defective behavior and provided new DFT direction.• Developed and implemented logic built-in self-test (BIST), Design-for-Test (DFT) features for IBM MCM chips.