1 Verifying the ble link layer event control logic by building a BLE master&slave host model and the test bench(verilog based) with MCU firmware coding. Writing test cases to meet the line,condition, fsm and functional coverage2 Build various testbenches for one master and one slave, one master with two slaves, one slave and two masters etc.3 Prepare test pattern and test plan for CP test4 Running FPGA flow (Altera based) for application engineer testing.

1 RTL coding modification for the bus of network processor IP. The bus is connected multiple cores and co-processors. The funiciton of the bus is to transfer the speecific command from a core to a dedicated co-processor. The architecture of the bus is based on cross bar and the arbitration mechanis is baded on RR. 2 RTL coding modifcation for SMMU from ARM to meeting the timing requirement. 3 RTL coding for PIPE 3.0 PCS (interface between MAC and PHY) for PCIE. The modules for RTL coding are 128/130 encodling, symbol align and Elastic buffer for timing compesation.