David Zambelli Email and Phone Number
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More than twenty years experience working in microelectronic companies.Technical experiences in design, implementation and physical verification of all that's related to the layout of IC stand-alone devices using CMOS technologies from 0.6 um until 45/41 nm. Many are the devices feasibility studies, Die size evaluations, devices implementation, finishing phases and work flows where I had possibility to work on and many are the projects where I had the responsibility to release the device on time respecting all the required design aspects.Thorough knowledge on the work environment and the related CAD tools.Good attitude to train newcomers complete my job profile.
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Ic Senior Layout DesignerStmicroelectronics Jul 2014 - PresentAgrate Brianza -
Ic Physical DesignerMicron Technology May 2010 - Jun 2014Agrate B. - Folsom (Ca-Usa)PadOut evaluation in order to fit device into assigned packagesFloorplanning/power plannig and routing macro blocks using PulsicVoltage Drop static analysis and EM analysis using TotemWork environment customization for Pulsic and Totem toolsAnalog/digital layout of FLASH NOR SPI devices : base blocks, macro blocks and whole fullchip- rowdec, sense amp, currgen, switches, ESD structures, pad structures, pumps, apr interface, glue logic.- analog base block layout guidelines based on matching devices methodology concept.DFM methodology implemented both in layout baseblocks realization and routing Physical verification (LVS/DRC/Ant/Soft/density) as required by technology, using Calibre/HerculesNewcomers training on 'Pulsic' tools and floorplan/power plan methodologiesNewcomers traning on 'Totem' tools in order to perform IR drop static analysis and EM analysisTechnology node : 45nm - flash NOR -
Senior Layout EngineerNumonyx Apr 2007 - Apr 2010Agrate B.Analog/digital layout of FLASH NAND PARALLEL devices : base blocks, macro blocks- page buffer, currgen, bandgap, switches, standard cells, pumps, apr interface, glue logic.- analog base block layout guidelines based on matching devices methodology conceptPhysical verification (LVS/DRC/Ant/Soft) as required by technology, using CalibreTechnology node : 41nm - flash NAND -
Layout Engineer Team LeaderStmicroelectronics Mar 2004 - Mar 2007ArzanoNewcomers training for start-up layout team.Analog/digital layout of FLASH NOR PARALLEL devices : base blocks, macro blocks and whole fullchip- array, coldec, rowdec, sense amp, currgen, bandgap, switches, ESD structures, pad structures, standard cells, pumps, apr interface, glue logic.- analog base block layout guidelines based on matching devices methodology concept.Layout development of a entire standard cell library in T9LX process. Fullchip floorplan development.Physical verification (LVS/DRC/Ant/Soft) as required by technology, using CalibreParasitic extraction using Arcadia/StarRCWork environment customizationTechnology node : 65nm, 90nm, 110nm - flash NOR
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Memory Design EngineerStmicroelectronics Nov 1999 - Feb 2004Agrate B.Develop memories generator ROM/RAM - Critical path spice simulation using eldo - Schematic editor using opus - Base blocks layout : core, rowdec, coldec, sense, glue logic - Physical verification LVS/DRC using calibre - Functionality verification using powermill - Java code development to assembly layout and schematic leaf blocksTest chip assembly - routing blocks using Silicon Ensamble - timing driven analysis using constraints filesTechnology node : 180nm, 350nm - mixed A/D
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Layout EngineerStmicroelectronics Jul 1993 - Oct 1999Agrate B.Analog/digital layout of EPROM devices : base blocks, macro blocks and whole fullchip - array, coldec, rowdec, sense amp, currgen, bandgap, switches, ESD structures, pad structures, standard cells, glue logic. - analog base block layout guidelines based on matching devices methodology concept.Fullchip floorplan development.Physical verification (LVS/DRC/Ant/Soft) as required by technology, using Diva and Dracula.Newcomers training.Technology node : 600nm --> 400nm (shrink) - EPROM
David Zambelli Skills
David Zambelli Education Details
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Technician Of Industrial Automation Design And Integrated ManufacturesIndustrial Automation -
Itis (Technical Institute - Electronics)Industrial Electronics
Frequently Asked Questions about David Zambelli
What company does David Zambelli work for?
David Zambelli works for Stmicroelectronics
What is David Zambelli's role at the current company?
David Zambelli's current role is IC Senior Layout Designer at STM.
What is David Zambelli's email address?
David Zambelli's email address is david.zambelli@st.com
What schools did David Zambelli attend?
David Zambelli attended Technician Of Industrial Automation Design And Integrated Manufactures, Itis (Technical Institute - Electronics).
What are some of David Zambelli's interests?
David Zambelli has interest in Hiking And Outdoor Life, Motor Biker, Read Novels, Alpinism.
What skills is David Zambelli known for?
David Zambelli has skills like Floorplanning, Layout, Virtuoso Xl, Unix, Parasitic Extraction, Design For Manufacturing, Physical Verification, Ir Drop Static Analysis, Layout Verification, Design Environment, Ic, Dfm.
Who are David Zambelli's colleagues?
David Zambelli's colleagues are Vincenzo Randazzo, Walter Chen, Loic Baudoin, Daniel Colonna, Mohd Rizvi, Evelina Castaldo, Corine Bousquet.
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