David Barrow Email & Phone Number

Chapel Hill, NC, US

Santa Clara, CA, US

San Jose, CA, US

Verification and Design Engineer. Responsible for UVM test environments of FPGA designs used to explore the behavior of DDR memories (2/3/4/LP4) at LN2 temperatures. The Cadence and Xilinx tool flow used make, Perl, and TCL scripts to automate building RTL, creating common test components, and to automate the compile and simulate steps.Worked closely with.

San Jose, California, US

Verification Engineer. Created UVM test environments including test components (checkers, scoreboards and reference models) for a memory controller to transfer data to/from a DDR4 RDIMM board to FLASH memory in the event of a power failure. AXI4lite, APB VIP and a FLASH memory model were used to generate and/or monitor traffic on the DUT. Wrote C code for.

Design Verification using SystemVerilog (OVM/UVM) and OpenVera. Responsible for UVM test environments of several OTN Optical Transport chips. ONT-400 (750-million gate ASIC): created the UVM environment and test cases for a dynamic time slot processor to process ODU0 to ODU4 traffic as well as Segmentation and Reassembly (SAR). OTN-100 (75-million gate.

Design Verification using Vera, Verilog and SVA. Brought on-board to finish the verification of a 45-million gate ASIC for OTN-40. Wrote directed tests to verify the OTN overhead and alarm processing unit.

Geneva, Geneva, CH

Design and Verification of AMBA3 (AXI) DMA controllers consisting of up to 4 masters and 128 virtual channels operating at 208 MHz using VHDL, Mentor Graphics and Specman 'e'. Design and Verification of AMBA3 (AXI) DMA controller consisting of a single master and 4 virtual channels for the UniPro interface using VHDL and Mentor Graphics.

Defined and developed in-house IP such as a MSL based IPC, a AMBA AHB DMA controller with dual masters and 64 virtual channels, an IPC for EDGE protocol processor, an ARM7/9 MMU accellerator and a AMBA AXI DMA controller with quad masters and 128 virtual channels. Developed test benches in VHDL, Specman e and SystemVerilog languages. Participated in.

Kista, Stockholm, SE

Architectural definition of TDMA Baseband processors. Defined and developed several in-house IPs such as a programmable RAM based timing engine, a secure interface box to update cell phone SW and a DRAM controller.

Designed and developed the hardware based text search engines for the flagship product of this company. Development included schematic capture, PCB layout, FPGA/PAL/PLA synthesis and lab work using logic analyzers and oscilloscopes.

Shepherded customers designs through GE's design flow for gate-arrays. Tasks included logic design, gate-array layout and design testing and verification after manufacture.