Dave Lim Email & Phone Number

Cambridge, Cambs, Gb

Cambridge, Cambs, Gb

RTL Design

Austin, Texas, Us

Working on Project RAPID, a hardware-software co-design project targeting large-scale data management. Worked on Floating Point Add/Sub unit capable of Double/Single/Half precision and SIMD variants.

Santa Clara, California, Us

Broxton - System on Chip (2013 - 2014) • Managed the System Agent (SA) team in the memory fabrics. Team consisted of 20+ members across Architecture, Design, and Verification• Developed implementation schedule, deliverables, and resource allocation • Mentored junior members in best design practices• Enabled configurability to the design through hardware and/or software configurations• Provided timing, area, and power growth estimations• Mitigated silicon timing paths through architectural re-pipelining • Key reviewer of high level architectural specification for the SA• Ensured power and reset protocols adhered to spec• Implemented clock gating and power gating techniques to converge to power targets• Added complex DFT features to help Post-SI debugCrystal Well - Client PC (2011-2012)• implementated the extended last level cache (eLLC). A tag lookup unit for a high density L4 cache, shared between CPU and GPU• Implementation included SECDEC, row redundancy, and flow changes for memory transactions• Designed novel approach to clear X’s simultaneously between the smaller L3 and L4 cache tag array structures to save hardware and reset cycles• Pioneered 3-step compilation model builds to save model build times at the cost of simulation runtime penalties• Conceptualized software Drove software team to develop tools for individual RTL coders to make use of automated infrastructure to build models and run test regressions• Helped identify speedpaths on silicon and found an open latch in the design• Coordinated RTL Models when project lead not available

Santa Clara, California, Us

Haswell / Broadwell – Client PC (2008-2011) • Led investigation of the feature changes in the Register Allocation Table (RAT) for Transactional Synchronization eXtensions (TSX)• Close collaboration between Arch, Design and Verification Teams to reduce the scope of changes while maintaining desired performance metrics prior to implementation• Scheduled resources and completion deadlines for the components of the feature• Owned documentation spec for the RAT• Microarchitecture expert for backend custom circuits team• Fixed Post-SI speedpaths for RAT. Manual circuit changes in custom data path and synthesized designs.• Lint cleanup duties to ensure readable/synthesizable codeNehalem / Westmere – Client PC (2006-2008) • Synthesized functional blocks using Synopsys DC, ICC and internal customized tools• Converged timing, power and area constraints of functional blocks using custom static timing analysis and power estimation tools• Implemented various clock gating and logic simplifications to reduce power consumption • Owned model syncs between cluster and core code repositories• Automated repeated tasks with scripting tools• Ensured circuit design matches RTL with customized tools built with Cadence Conformal Tools.• Verification of X-Free circuit designs using custom internal tools

Santa Clara, California, Us

Developed a software tool call Array Dump, a debug tool written in C++/Perl used to shift array data through the Test Access Port (TAP).Developed a software tool called CRGen, a Perl script that extrapolates control register definition XML files and converts them to various formats such as RTL, text, and webpages