David Chen Email & Phone Number

Palo Alto, Ca, Us

Palo Alto, California, Us

Co-Founded the Digital Health Startup and Served as Chief Technology Officer• Co-invented the core technology (4 patents issued) for a disruptive consumer product that acquires bio-signals, classifies/predicts mental states, and delivers corresponding stimuli as “training wheels” to guide novice and intermediate meditators to the “mindful state”• Established the company, developed the corporate strategy, built the advisory board with psychiatrists & neuroscientists teaching at Harvard Medical School and UC Davis, and instituted clinical trials by collaborating with a University of Toronto teaching hospital• Built and directed a global team of data scientists to develop & integrate emerging technologies including Machine Learning (ML), human-computer interaction / interface (BCI), Internet of Things (IoT) and open-source software; Led the product development, and successfully classified brainwaves from In-Ear EEG prototypes

Palo Alto, California, Us

• Defined minimum viable product (MVP) requirements, provided product vision, specified value proposition and market size based on Lean Startup Method and primary/secondary studies, and gained traction with venture capitalists (VC) with quantitative analyses

San Jose, Ca, Us

* Delivered special designs per customer's request.* Built China Design Center.* Acted as a liaison to APAC FAEs and customers to HQ.* Enabled semiconductor companies to rapidly and cost effectively innovate, differentiate and win in their markets.* Combined hardware innovation with software tools and customer support to provide high-value programmable solutions to customers worldwide.* Built and led a global team of highly skilled managers and flexible engineers to innovate, execute and deliver on time with high quality.* Oversaw definitions, micro-architectures, logic designs, system simulations and documentation for DSP IP’s, to create IP databases ready for integration.* Performed all aspects of IP definition-to-delivery flow, from micro-architecture to RTL coding, verifications, logic synthesis, physical layout (place and route), performance (timing), power and area (PPA) closures and documentation.* Established operation infrastructures, conducted experimental tests, evaluated results, to select between alternative micro-architectures and/or implementations, for superior PPA results.

San Jose, California, Us

Delivered Industry’s 1st Artificial Intelligence (AI) Deep Learning (DL) Digital Signal Processor (DSP)• Delivered all the world’s #1 licensed DSP’s for successful ADAS, 5G mobile, VR, AR & XR visualizations, entertainment, radar, edge AI or other edge computing accelerations• Mapped software algorithms to hardware, specified Scalar and Single Instruction-Multiple Data (SIMD) Vector Floating-Point (FP, VFP) Instruction Set Architecture (ISA), micro-architected, implemented and benchmarked RTL which takes only 10-15% DSP area and achieving the same MAC/cycle with 15-30% lower power compared to fixed-point to further the company’s leadership• Authored publications and reviewed presentations for Linley Processor Conference• Built the DSP design team with ~10 engineers in Silicon Valley and India for Tensilica® (acquired by Cadence® in 2013), and controlled schedule and resources• Developed and promoted high-performing individuals to create an energetic environment and to grow productivity• Worked with strategic customers on IP requirements, supervised transfer of completed products, and supported for production• Resolved a difficult analog/digital bug and saved the company’s only Mobile World Congress (MWC™) demonstration

San Jose, Ca, Us

(now part of Microchip Technology)• Earned 18th Annual EDN Innovation Award and Portable Design Editor’s Choice with All-in-OneMemory. Managed entire product life cycles of All-in-OneMemory, by prioritizing according to customer requirements, market trends, company strategy, and resources.• Managed multiple concurrent cross-functional projects through carefully establishing, tracking and resolving project costs/schedules/resources/risks; Secure commitments from Software/Technology/Engineering Services/Publications/Marketing/Operation; Fostered strong cooperation with internal and external resources; Mitigated risks and unanticipated events.• Delivered first-pass silicon success without any logic or timing flaws, using in-depth spec-to-testing experience and lessons learned from prior projects, and through carefully selecting and enforcing design/verification/synthesis/DFT/layout/STA practices, inserting new technologies and tools, conducting design audits, and resolved characterization and production issues.• Directed low-power secure embedded NAND-based memory subsystem developments, through defining design scopes, developing architecture, trading off between various analog IP cores, selecting vendors, assigning development tasks, reviewing VLSI micro-architecture proposals/specs/coding, auditing RTL implementation, and managing prototype bring-up.• Led debug engineering hands-on. Perform analytical problem solving, to quickly identify excessive IR drop, and to increase yield by using power-aware scans. Set day-to-day debug direction and drove resolutions according to project priorities. Acted as an engineer during emergency.• Aligned engineering team through hands-on leadership, to produce best works on multiple parallel projects, through recruiting, training, mentoring, coaching, workload balancing, setting group and individual goals, and managing performance. Managed across geographically dispersed cross-functional teams and offshore resources.

Hsinchu City, Tw

• Supported Design IP by working effectively with customers, CAD tool vendors, Sales and Marketing, to ensure delivery of USB and other mixed signal IP. Managed across geographically dispersed cross-functional teams to guarantee signal integrity at design, layout, package, board and testing stages. Prepared and participated in weekly customer meetings. Presented program status to senior managements of both sides. Created technical documents and managed technical releases.• Productized multiple RTL hand-off projects through directing design and support resources abroad and in-house, as well as scheduling, prioritizing, coordinating and supervising engineering tasks. Completed implementation from synthesis thru post-layout verification and tapeout. Optimized synthesis scripts to maximize design performance. Ran static timing analysis (STA) to verify post-layout convergence.• Retained key customer through patiently and diligently resolving communication and technical issues, and proactively identified critical testability and manufacturability problem to avert re-spin for customer.

New York, Ny, Us

• Consulted and educated professional investors on industry trends and latest technologies, products and services. Clients include Bear Stearns, Fidelity and others.

Ca

• Productized (FCS) three releases of VLSI for $14 million program on original schedules. The chip is the core engine inside Nortel secured VPN product line OPTera Metro 1200, 1400 and 1450. The OPTera Metro family has been deployed by AT&T, KPN among others.• Performed scheduling and reviews. Determined and drove new design/verification methodology and digital architecture. Created and executed detailed development and test plans.• Mitigated risks of complex FPGA / ASIC projects by utilizing strong technical expertise to anticipate unplanned challenges, to develop mitigation plans, and to remove difficult obstacles within the team and cross-functionally in multiple product developments.• Accelerated development speed by approximately 20% by evaluating, defining, integrating and standardizing new high speed front-end digital design processes, EDA tools, design rules and verification methodology to handle 32,000 lines of RTL codes or 2 M gates.• Rescued $1.8 million revenue and saved key customer. Averted product returns by quickly isolating elusive system-level fault and implementing urgent patch solution.

• Managed and led system-on-chip (SOC) engineering. Evaluated, selected and coordinated offshore foundry, contract manufacturers, test and assembly house, and ASIC back-end vendor. Interfaced with internal mechanical, electrical, and firmware developers.• Specified, architected, developed and verified mixed-signal standard-cell SOC ASIC. Designed reusable IP cores. Performed Verilog HDL integrations, simulations, verifications and syntheses. Supervised clock tree synthesis (CTS) and layout. Conducted pre- and post- layout static timing analysis (STA) and optimization. Closed full-chip SDF timing issues.

Santa Clara, California, Us

• Revitalized 733 MHz 4MB level-3 (L3) cache snooper on 25-million-transistor CPU by re-microarchitecting fully-pipelined FSM to hide memory latency, and to incorporate ECC.• Saved over 12 man-months of effort by reestablishing timing environment modules for BUS cluster on Intel Architecture 64 bits (IA-64) superscalar Itanium® full-custom .18 micron microprocessor.• Ensured meeting chip operating frequency goals by testing and certifying Synopsys® synthesis scripts for use by over 100 logic designers.• Debugged Pentium MMX IA32 microprocessor using component debug testers, through cross-site/cross-division engagements.

Bs, Cs

Ms (Coursework), Computer Engineering