David Chen Email & Phone Number

Palo Alto, CA, US

Palo Alto, California, US

• Co-Founded the Digital Health Startup and Served as Chief Technology Officer
• Co-invented the core technology (4 patents issued) for a disruptive consumer product that acquires bio-signals, classifies/predicts mental states, and delivers corresponding stimuli as “training wheels” to guide novice.
• Established the company, developed the corporate strategy, built the advisory board with psychiatrists & neuroscientists teaching at Harvard Medical School and UC Davis, and instituted clinical trials by collaborating.
• Built and directed a global team of data scientists to develop & integrate emerging technologies including Machine Learning (ML), human-computer interaction / interface (BCI), Internet of Things (IoT) and open-source.

Palo Alto, California, US

• Defined minimum viable product (MVP) requirements, provided product vision, specified value proposition and market size based on Lean Startup Method and primary/secondary studies, and gained traction with venture.

San Jose, CA, US

* Delivered special designs per customer's request.* Built China Design Center.* Acted as a liaison to APAC FAEs and customers to HQ.* Enabled semiconductor companies to rapidly and cost effectively innovate, differentiate and win in their markets.* Combined hardware innovation with software tools and customer support to provide high-value programmable.

San Jose, California, US

• Delivered Industry’s 1st Artificial Intelligence (AI) Deep Learning (DL) Digital Signal Processor (DSP)
• Delivered all the world’s #1 licensed DSP’s for successful ADAS, 5G mobile, VR, AR & XR visualizations, entertainment, radar, edge AI or other edge computing accelerations
• Mapped software algorithms to hardware, specified Scalar and Single Instruction-Multiple Data (SIMD) Vector Floating-Point (FP, VFP) Instruction Set Architecture (ISA), micro-architected, implemented and benchmarked.
• Authored publications and reviewed presentations for Linley Processor Conference
• Built the DSP design team with ~10 engineers in Silicon Valley and India for Tensilica® (acquired by Cadence® in 2013), and controlled schedule and resources
• Developed and promoted high-performing individuals to create an energetic environment and to grow productivity

San Jose, CA, US

• (now part of Microchip Technology)
• Earned 18th Annual EDN Innovation Award and Portable Design Editor’s Choice with All-in-OneMemory. Managed entire product life cycles of All-in-OneMemory, by prioritizing according to customer requirements, market.
• Managed multiple concurrent cross-functional projects through carefully establishing, tracking and resolving project costs/schedules/resources/risks; Secure commitments from Software/Technology/Engineering.
• Delivered first-pass silicon success without any logic or timing flaws, using in-depth spec-to-testing experience and lessons learned from prior projects, and through carefully selecting and enforcing.
• Directed low-power secure embedded NAND-based memory subsystem developments, through defining design scopes, developing architecture, trading off between various analog IP cores, selecting vendors, assigning.
• Led debug engineering hands-on. Perform analytical problem solving, to quickly identify excessive IR drop, and to increase yield by using power-aware scans. Set day-to-day debug direction and drove resolutions.

Hsinchu City, TW

• Supported Design IP by working effectively with customers, CAD tool vendors, Sales and Marketing, to ensure delivery of USB and other mixed signal IP. Managed across geographically dispersed cross-functional teams to.
• Productized multiple RTL hand-off projects through directing design and support resources abroad and in-house, as well as scheduling, prioritizing, coordinating and supervising engineering tasks. Completed.
• Retained key customer through patiently and diligently resolving communication and technical issues, and proactively identified critical testability and manufacturability problem to avert re-spin for customer.

New York, NY, US

• Consulted and educated professional investors on industry trends and latest technologies, products and services. Clients include Bear Stearns, Fidelity and others.

CA

• Productized (FCS) three releases of VLSI for $14 million program on original schedules. The chip is the core engine inside Nortel secured VPN product line OPTera Metro 1200, 1400 and 1450. The OPTera Metro family has.
• Performed scheduling and reviews. Determined and drove new design/verification methodology and digital architecture. Created and executed detailed development and test plans.
• Mitigated risks of complex FPGA / ASIC projects by utilizing strong technical expertise to anticipate unplanned challenges, to develop mitigation plans, and to remove difficult obstacles within the team and.
• Accelerated development speed by approximately 20% by evaluating, defining, integrating and standardizing new high speed front-end digital design processes, EDA tools, design rules and verification methodology to.
• Rescued $1.8 million revenue and saved key customer. Averted product returns by quickly isolating elusive system-level fault and implementing urgent patch solution.

• Managed and led system-on-chip (SOC) engineering. Evaluated, selected and coordinated offshore foundry, contract manufacturers, test and assembly house, and ASIC back-end vendor. Interfaced with internal mechanical.
• Specified, architected, developed and verified mixed-signal standard-cell SOC ASIC. Designed reusable IP cores. Performed Verilog HDL integrations, simulations, verifications and syntheses. Supervised clock tree.

Santa Clara, California, US

• Revitalized 733 MHz 4MB level-3 (L3) cache snooper on 25-million-transistor CPU by re-microarchitecting fully-pipelined FSM to hide memory latency, and to incorporate ECC.
• Saved over 12 man-months of effort by reestablishing timing environment modules for BUS cluster on Intel Architecture 64 bits (IA-64) superscalar Itanium® full-custom.18 micron microprocessor.
• Ensured meeting chip operating frequency goals by testing and certifying Synopsys® synthesis scripts for use by over 100 logic designers.
• Debugged Pentium MMX IA32 microprocessor using component debug testers, through cross-site/cross-division engagements.

Bs, Cs

Ms (Coursework), Computer Engineering