Advanced semiconductor packagingFull-chip planning and implementationFlow and methodology development

Partition-level physical designC4 bump planning/placement tool/methodology developmentTape-outs at 28nm and 5nm

Owned physical design for designs in 20nm, 16nm, and 14nm process nodes.

* Owned physical design for two blocks (1M and 2M gates) on a 28nm Silicon processo APR using Synopsys ICC and Mentor Olympuso Evaluated floor-plan bounds and block interfaces, implemented timing-driven placement/routing, developed/implemented/evaluated experiments to balance area with physical/timing convergenceo Evaluated relative strengths of APR design tools to choose the correct production solution

Senior Design Engineer (2009 – 2012):• Taped out designs from 250nm to 22nm nodes• Led floor-plan design and implementation in Synopsys ICC.o Developed / implemented Layout Convergence methodology and flowso Area assignment, interface definition, floor-planning, auto-place-and-route, ECOs, design rule clean-up using ICC• Utilized ICC P&R system to support layout audits• First-line manager of mask design teams o Technical oversight, mentoring, work assignment, status tracking and proactive guidance• Coordinated and instantiated FAB-required layout (scribe, metrology, edge monitors). • Developed interface tools and methodology to design C4 bump placement at arbitrary physical hierarchyo Coordinated work in Synopsys ICC, Mentor Expedition, Cadence Allegro)o C4 bump placement/assignment/verification across Silicon / Package / Board teamso Data-collection and analysis scripts in TCL, PERL, CSHSenior Design Engineer (1998 - 2008):• Led floor-plan team using internally-developed CAD tools• Drove development and implementation of Layout Convergence methodology and flows• C4 interconnect definition, established procedures for cross-team verificationDesign Engineer (1987 - 1998):• Dada queue micro-architecture, RTL code, logic design, and timing convergence• Generated circuit design guidelines• Evaluated external circuit designs for high-bandwidth memory interfac• Analyzed circuits, taped out test chip, planned/performed/documented experiments to verify predictions • Expanded Register File design to support more access ports and more bypass conditions• Updated RTL code (pre-Verilog language) and schematics (internal CAD tool), verified them in behavioral and logic simulators, verified circuit-design changes with new circuit simulation environment.• Developed micro-architecture, RTL code (pre-Verilog language), logic design, and circuit design• Verified design using behavioral, logic, SPICE simulators, static timing analysis (internal CAD tool)

Design Engineer• Converted multi-chip circuit modules into single-chip solutions using design suite from VLSI, Inc.• Generated specification, design, and documentation for cell-based custom and standard-cell CMOSintegrated circuits (two designs through fabrication, first-pass success)• Used VLSI Technology design system, SPICE circuit analysis; managed Apollo workstation network

Design Engineer• Performed ECOs on custom integrated circuits using CALMA layout system, MTIME circuit analysis• Designed CMOS gate array for portable cellular telephone (first-pass success)• Designed, debugged, and maintained breadboards, supported assembly-language debug monitor• Generated assembly-language test programs and test procedures for custom IC’s and modem module