David Seefeldt Email & Phone Number

Senior ASIC / FPGA engineering professional with extensive experience in both design and project engineering. Background includes VHDL RTL design, RTL and gate simulation, synthesis, static timing, FPGA place and route, and ASIC emulation using Synopsys' Certify and Identify. Designs that met DO-254 Dal-A.Success in new designs and enhancing existing designs with new features and performance improvements. In house instructor for various design tools at several companies.Specialties: EDA Tools: FPGA design using Questasim(Modelsim), Synopsys' Synplify_Pro, Altera’s Quartus, MicroSemi(Actel) Designer, and Xilinx. ASIC emulation using Synopsys' Certify, Identify and Synplify_Pro. ASIC Design using Questasim(Modelsim), Primetime, Design Compiler, and Palladium. Taught in house class on Static Timing concepts and TimeQuest.Version control: SOS, RCS, PVCS Subversion.Languages: VHDL RTL, Verilog RTL and gates, and Tcl.Operating Systems: Unix/Linux and Windows.Lab: Oscilloscope, logic analyzer, waveform generator and ICE DiNi ASIC emulation system.

Listed skills include Tcl, Modelsim, Eda, Logic Analyzer, and 46 others.