David Sekel Email & Phone Number

* Brought advanced CMOS process technologies from development into production through electrical and physical failure analysis of time zero, (HTOL) high‐temp operating life, and commercial and automotive qualification failures. * Experienced in taking different types of products during process development stage from 0% to yielding for transfer into production facility.* Trained and mentored engineers and technicians on advanced CMOS process flow improvements, device operation, and analysis techniques.

* Managed 180nm node HTOL setup, read point execution, electrical and physical failure analysis, characterization, and reliability database documentation, with emphasis on continuous improvement in cost and automated data analysis.* Supervised three engineers to support reliability test, electrical, and physical failure analysis in support of new process qualifications.* Implemented job function for Quality Reliability Engineering technicians, including expectations and certification procedures to operate Teradyne J971, and general test support expectations for plastic package and reliability assessment efforts.

* Provided electrical and physical failure analysis support for CMOS process development, de‐layering recipe development, and improved polishing technique for viewing under bump metalization of solder balls for package reliability failures.* Performed data analysis support and worked with test engineering to improve logical to physical mapping for DSP internal memories.* Led Quality Improvement Team, and reduced Physical Failure Analysis lab cycle time by 20%.* Reverse engineering of competitor parts.* Bump process integration, worked with vendors to develop whole wafer bump height measurement system. Identified metrology tools and equipment necessary to support upgrading internal bump facility to eight inch capability.

Bachelor Of Science, Electrical Engineering

Education record