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A technically oriented and results-driven engineering professional with extensive experience in CMOS processes, plastic package and flip-chip process flows, reliability issues, yield improvement, staff and vendor management, and using schematics and layouts to facilitate defect isolation. Leverages practical experience with strong communication skills to work well with all levels of an organization. Isolates failures and identifies fail mechanisms on advanced semiconductor devices.
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Product Engineering - Failure AnalysisTexas Instruments 2001 - 2015* Brought advanced CMOS process technologies from development into production through electrical and physical failure analysis of time zero, (HTOL) high‐temp operating life, and commercial and automotive qualification failures. * Experienced in taking different types of products during process development stage from 0% to yielding for transfer into production facility.* Trained and mentored engineers and technicians on advanced CMOS process flow improvements, device operation, and analysis techniques. -
Reliability And Package Test Support Section ManagerTexas Instruments 1997 - 2001* Managed 180nm node HTOL setup, read point execution, electrical and physical failure analysis, characterization, and reliability database documentation, with emphasis on continuous improvement in cost and automated data analysis.* Supervised three engineers to support reliability test, electrical, and physical failure analysis in support of new process qualifications.* Implemented job function for Quality Reliability Engineering technicians, including expectations and certification procedures to operate Teradyne J971, and general test support expectations for plastic package and reliability assessment efforts. -
Product EngineeringTexas Instruments 1980 - 1997* Provided electrical and physical failure analysis support for CMOS process development, de‐layering recipe development, and improved polishing technique for viewing under bump metalization of solder balls for package reliability failures.* Performed data analysis support and worked with test engineering to improve logical to physical mapping for DSP internal memories.* Led Quality Improvement Team, and reduced Physical Failure Analysis lab cycle time by 20%.* Reverse engineering of competitor parts.* Bump process integration, worked with vendors to develop whole wafer bump height measurement system. Identified metrology tools and equipment necessary to support upgrading internal bump facility to eight inch capability.
David Sekel Skills
David Sekel Education Details
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Electrical Engineering -
Meadville Area Senior High
Frequently Asked Questions about David Sekel
What is David Sekel's role at the current company?
David Sekel's current role is Inside Sales Manager.
What is David Sekel's email address?
David Sekel's email address is d-sekel@ti.com
What schools did David Sekel attend?
David Sekel attended The University Of Texas At Arlington, Meadville Area Senior High.
What are some of David Sekel's interests?
David Sekel has interest in Children, Education.
What skills is David Sekel known for?
David Sekel has skills like Failure Analysis, Semiconductors, Cmos, Ic, Semiconductor Industry, Product Engineering, Analog, Characterization, Mixed Signal, Microelectronics, Electronics, Silicon.
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David Sekel
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Dave Sekel
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