ISU Power 9 processor design ownership: fixed and floating point register rename facilities (Unified Mapper)- Creation and presentation of High Level Design documentation- Low level design development and implementationOwnership of ISU unit top level VHDL and pervasive functionCore ISU representative for Power 8 hardware validation- Fail triage and debug bexploration- Test plan development and ownership- Creation of hardware irritators for in-depth testingOwnership of legacy logic for the following P8 and P7 design areas:- Unified Mapper (fixed and floating point register rename)- Small Mappers (special purpose register rename)- Branch and Condition Register Logic Instruction Issue QueuesNew hire and intern mentorship

Power 8 Core logic ownership: Small Mappers (Special Purpose Register Rename)- Expanded design from 4 to 8 threads- Added capability to handle Dispatch and Completion on two threads simultaneously- Combined macros and eliminated unused legacy logic- Actively drove down timing on slow circuits. Redesigned logic to meet timing where necessary.- Documented the design Power 8 Synthesis- Ownership of 4 large synthesized macros across two functional units- Worked with IBM Research and EDA teams, enhancing synthesis tools to handle difficult special case scenarios in the largest macros- Execution of automated and manual circuit fixes for Engineering Change Orders and late bug fixesPower 7 Core logic ownership: Branch and Condition Register Logic Instruction Issue Queues- Implementation of new features and pipeline timing, such as enhancement of branch conditional execution- Drove down timing and redesigned logic as necessary to solve timing issuesPower 7 Synthesis- Ownership of numerous small synthesized macros- Execution of automated and manual circuit fixes for Engineering Change Orders and late bug fixesTorrent Processor Integration- Performed synthesis under new, experimental methodology- Worked with IBM Research and EDA teams to specialize synthesis and integration tools for special case macros

Cell BE Processor logic ownership: SMC Memory Management Unit- Memory address translation for the Cell SPU cores- Developed and implemented logic for the front half of the translation pipeline- Took ownership of entire unit for DD2.0 and beyond- Documented design for the Book IV Workbook- Involvement with unit macro placementCell BE Synthesis- Ownership of macro synthesis across multiple units- Leadership of synthesis methodology for the processorCell BE Test Chip- Wrote verification checkers in the C language model test environment for the SPU core- Wrote the pervasive scan logic for SPU core using Perl to automatically generate VHDLCell BE Characterization- Developed high power graphic sequences to measure peak power usage- Tested and compared power and max speed over various manufacturing variables such as silicon doping