David Chodelka Email & Phone Number

Princeton, NJ

Hands on leader of a team of highly skilled and diverse Electrical (EE) and Mechanical Engineers (ME) focusing on products for High Performance Imaging/Cameras, Biometric Identification Products - Iris/Face/Fingerprint, Security Devices, and Video Processing products. EE Team spans knowledge areas including: Analog/RF design, Electronic Board Design, FPGA.

Princeton, NJ

Led a team of highly skilled and diverse Electrical Engineers focusing on products for High Performance Imaging/Cameras, Iris Recognition and Identification Products (IOM), Security Devices, and Video Processing products. Team spans knowledge areas including: Product/System Design, Analog/RF design, Electronic Board Design, FPGA Design, and Digital ASIC.

Princeton, NJ

Project Lead for product family featuring advanced video processing technology pioneered at SRI (Sarnoff). The product utilized DSP based video stabilization technology to provide low cost world class performance. Products also included Video over IP encoder technology for use on UAVs. Worked closely with Marketing to define products and support customer.

Yardley, PA

• Team leadership responsibilities focused on the management of the World-wide Broadcom DTV Physical Design team. Responsibilities included: project coordination/planning, team development, mentoring/coaching site.
• Delivered seven tape outs, most recently six 40 nm tape outs ranging in design size from 200M to 500M+ transistors for the DTV market. Designs all contained a variety of mixed signal IP: DDR, ENET, USB, LVDS, ADCs.
• Increased STD Cell Utilization by 5-8%, resulting in smaller die sizes and lower product cost. DTV was a very cost challenged and competitive market so emphasized lowest cost in physical design process by challenging.
• Worked closely with the 40 nm timing recipe team to ensure to all the requirements and tracked and managed the full chip timing closure issues, driving each to a solution.
• Established sign-off checklists to ensure all activities were completed correctly at each phase of the project.
• Developed and implemented a power estimation spreadsheet accurate within 10%. The spreadsheet allowed for voltage, temperature and process variation scaling, based upon spice simulation data from the standard cell.

Functional Management responsibilities included: Synthesis to GDS for all Yardley products, device characterization/bring-up, Ops manufacturing ATE design/program, and FA/ product to EOL support. Devices designed during this time were built in 65 nm technology node. Devices were focused on Frame Rate Conversion for DTV panels – 60 to 120/240 Hz. Design.

Managed a team that is responsible for physical implementaion of IC's for the DTV and LCD Panel space of the consumer market. This included from synthesis through physical design to GDS, packaging, lab qualification, operations interface, customer FA's, and product end of life.

A start-up where I managed an ASIC design team, focused on the pioneering and development of Digital TV reception technologies for over cable and over the air (QAM/VSB), from architecture through GDS. Also managed the IT infrastructure for the entire company.

Responsible for the design of several ASICs for the Set Top Box market. (previously General Instruments)

Responsible for various successful ASIC designs for the set top box market - promoted from senior engineer to senior manager over the course of 9 years.

Worked on early pioneering of Disk Array technology, architecting and designing a prototype.

Developed ASICS for the instruction processor of a mainframe.

Bsee, Electrical Engineering

High School