David Chodelka Email & Phone Number

Princeton, Nj

Hands on leader of a team of highly skilled and diverse Electrical (EE) and Mechanical Engineers (ME) focusing on products for High Performance Imaging/Cameras, Biometric Identification Products - Iris/Face/Fingerprint, Security Devices, and Video Processing products. EE Team spans knowledge areas including: Analog/RF design, Electronic Board Design, FPGA Design, and Digital ASIC Design. ME Team spans knowledge areas including: ProE/Windchill & FlowWorks for design of systems including: Modeling, Product Design, Mechanical Enclosures, Thermal Analysis, Motor Systems, Optics and Spectrometers.Recent projects include: Iris Identity System for Airport Immigration/Gate, N-Glance (Iris Identity) Door System Cost reduction, Spectrometer for Fuel Cell Recharging Station Impurity Detection, Security IC for tracking counterfeit IC’s, 4kx4k Imager, Lidar ROIC, Imager Test Electronics utilizing Altera Cyclone V, Max10 as well as Xilinx Zynq 7020 and Kintex Ultra-scale devices.

Princeton, Nj

Led a team of highly skilled and diverse Electrical Engineers focusing on products for High Performance Imaging/Cameras, Iris Recognition and Identification Products (IOM), Security Devices, and Video Processing products. Team spans knowledge areas including: Product/System Design, Analog/RF design, Electronic Board Design, FPGA Design, and Digital ASIC Design.Team designed several projects including: A Hand Held Biometrics identification device using Embedded Quad Core Arm system running Android based applications with multiple HW boards that allowed Iris identification and enrollment at 2 meters distance; An embedded Iris Identification system for a high end door lock using an ARM SOC running bare metal SW system with a very low SWaP (battery operated) footprint; A test board/system and Command and Control function for a Space Application Imager – Star Tracking Application; And a 28 nm IC targeted at the security space – world’s smallest chip(?) @ 100x100um, employing RF power and interface control, OTP memory for portion of key storage and 256 AES encryption as part of the challenge/response sequence. Also led team efforts to improve tool flow and processes in order to better maintain and reuse our designs and advance overall team efficiency.

Princeton, Nj

Project Lead for product family featuring advanced video processing technology pioneered at SRI (Sarnoff). The product utilized DSP based video stabilization technology to provide low cost world class performance. Products also included Video over IP encoder technology for use on UAVs. Worked closely with Marketing to define products and support customer needs.Designed on-chip digital control logic for a Low Light CMOS HD Imager. Project Lead for DARPA Pixnet Low Light portion of a jointly developed EO/SWIR Fusion Camera system utilizing this Imager. Designed HW board and worked closely with the mechanical engineer to achieve a solution that met its target goals.

Yardley, Pa

Team leadership responsibilities focused on the management of the World-wide Broadcom DTV Physical Design team. Responsibilities included: project coordination/planning, team development, mentoring/coaching site managers, and working closely with technical experts to ensure successful product development.• Delivered seven tape outs, most recently six 40 nm tape outs ranging in design size from 200M to 500M+ transistors for the DTV market. Designs all contained a variety of mixed signal IP: DDR, ENET, USB, LVDS, ADCs, DACs, PLLs and OSC circuits. All designs were functional and first pass silicon successes. A key achievement was delivery of the first Broadcom 40 nm device into production. • Increased STD Cell Utilization by 5-8%, resulting in smaller die sizes and lower product cost. DTV was a very cost challenged and competitive market so emphasized lowest cost in physical design process by challenging the team to strive for the best area efficiency and set the standard for Broadcom in this area. • Worked closely with the 40 nm timing recipe team to ensure to all the requirements and tracked and managed the full chip timing closure issues, driving each to a solution.• Established sign-off checklists to ensure all activities were completed correctly at each phase of the project. • Developed and implemented a power estimation spreadsheet accurate within 10%. The spreadsheet allowed for voltage, temperature and process variation scaling, based upon spice simulation data from the standard cell library.

Functional Management responsibilities included: Synthesis to GDS for all Yardley products, device characterization/bring-up, Ops manufacturing ATE design/program, and FA/ product to EOL support. Devices designed during this time were built in 65 nm technology node. Devices were focused on Frame Rate Conversion for DTV panels – 60 to 120/240 Hz. Design size ranged from 125M to 225M transistors. Product FA support for our products required many customer facing meetings and presentations under challenging circumstances.

Managed a team that is responsible for physical implementaion of IC's for the DTV and LCD Panel space of the consumer market. This included from synthesis through physical design to GDS, packaging, lab qualification, operations interface, customer FA's, and product end of life.

A start-up where I managed an ASIC design team, focused on the pioneering and development of Digital TV reception technologies for over cable and over the air (QAM/VSB), from architecture through GDS. Also managed the IT infrastructure for the entire company.

Responsible for the design of several ASICs for the Set Top Box market. (previously General Instruments)

Responsible for various successful ASIC designs for the set top box market - promoted from senior engineer to senior manager over the course of 9 years.

Worked on early pioneering of Disk Array technology, architecting and designing a prototype.

Developed ASICS for the instruction processor of a mainframe.

Bsee, Electrical Engineering

High School