Dean Truong Email & Phone Number

Lowell, Ma, Us

Involved in transport products targeting wireline 100/400Gbps Single-Lambda Optical KR/SR/LR PHY applications.+DSP Hardware Design, Verification, and Validation of 100/400G (and beyond) Datacenter Optics.

+ Currently developing long range remote viewing techniques using modern alchemy and a focused study of Kabbalistic consciousness+ Previously worked as assistant researcher in crystallography under renowned chemist and Caltech alumnus, W. H. White Sr., Ph.D., and his colleague and J. P. Wynne High School alumnus, J. B. Pinkman

Santa Clara, Ca, Us

Involved in transport products targeting wireline 100/400Gbps Single-Lambda Optical KR/SR/LR PHY applications.+ Assisted in 100Gbps over Optical Channel 16nm FinFET PAM4 PHY solutions demo at European Conference on Optical Communications (ECOC) Sep. 2016.+ Assisted in 100Gbps over Optical Channel 16nm FinFET PAM4 PHY solutions demo at Optical Fiber Communications (OFC) Conference Mar. 2016.+ RTL design of AFE Calibration and DSP Monitoring for 16nm FinFET 100/400Gbps PHY Optical Channels used as IP and for SoC solutions.+ MATLAB+UVM Bitmatching Verification of Transceiver blocks such as PHY DSP Datapath and Debugging blocks.+ Python+UVM Verification and pre-Validation Test Infrastructure and Test Lab Management and Analog and FW Validation Chip bringup Infrastructure.+ Verified back-annotated SDF flow for back-end team for power estimation by collating silicon results (via homebrewed Python Validation and PyVISA instrumentation control).

Santa Clara, Ca, Us

Involved in transport products targeting wireline 10GBASE-T Copper and 100G Single-Lambda Optical KR/SR/LR PHY applications. Agressive tape-out and bringup schedules (approx. 1 Year from architecture to full chip bringup and customer demo).+ Bringup of Line-side 100Gbps PAM4 on 16nm PHY test chip (2 Month Bringup).+ Assisted in the End-to-End 28nm chip targeting 40Gbps on a SFP+ module to copper channel demo used at Optical Fiber Communication (OFC) Conference Mar. 2015.+ Bringup Host-side SERDES 4x10G to Line-side 1x40G PAM16/DSQ 28nm test chip (4 Month Bringup).+ Integrated an end-to-end power estimation flow for quick evaluation of DSP hardware architecture.+ Developed Verification, Power Estimation, and Validation Flow for DSP blocks targeting wireline PHY (less than 6 Months).+ Developed Micro-architecture and RTL for AFE Calibration and Timing Recovery (Clock Data Recovery) hardware (less than 6 Months).+ Defined and wrote DSP and configuration firmware functions and interrupts for debugging and characterizing the performance of a IEEE 802.3an 10GBASE-T Ethernet PHY test chip.+ Supported System Engineers with answers to their questions on the correct usage of the hardware and its interface via the firmware and the hardware abstraction layer.+ Developed a parameterized test scenario at the behavioral (RTL) level for electromagnetic interference (EMI) injection during data-mode; this was used to provide test coverage for an adaptive notch filter (during initial training) and fixed notch filter (during steady-state).+ Wrote scripts to autogenerate memory behavioral models for latched-based registers, and to parse and crawl through RTL code to classify RTL files as used versus unused.+ Verified a time-interleaved ADC gain and offset compensation algorithm and hardware implementation using System Verilog and MATLAB bit-matching and calibration performance tests that are mindful of pipelining and feedback details as well as external processor control.

Davis, California, Us

+ Measured on-chip power grid voltage switching and power-gating Ldi/dt noise caused by DSP cores, and tested noise suppression through the use of unused cores as reconfigurable decaps.+ Modeled processor architectures with MATLAB Simulink to derive optimal per-core adaptive voltage and frequency scaling control-theoretic algorithms for PVT/workload variation tolerance, manycore platform energy-efficiency, and application throughput robustness.+ Developed a energy- and area-efficiency framework for voltage and frequency assignment on manycore platforms with synchronous data flow based architectures.+ Wrote in assembly a medical ultrasound imaging front-/back-end receive-side processing application with over 1000 sub-tasks used to assess manycore efficiency under extreme task-parallelism.+ Analyzed performance of post-layout simulated power data of both a 16-bit DSP and a LDPC ASIC using Cadence NCVerilog and Encounter (via industry standard VCD & SDF files).+ Co-developed a source-synchronous timing model for circuit-switched on-chip networks.+ Characterized ring-oscillator frequency variation across multiple chips with an automated measurement Perl script interfaced with lab instrumentation through a Linux GPIB driver.

Davis, California, Us

+ Maintained the infrastructure of the lab including some IT support duties.+ Co-supervised changes in lab configuration and cubicle wall partitions.+ Kept an inventory of test equipment, and dealt with shipping for repairs/calibration.+ Advised the purchase of equipment and parts.+ Advised colleagues on research and publication submission selection.+ Edited the journal/conference manuscripts of colleagues for their technical content, style, grammar, and presentation before submission.

Davis, California, Us

Microcomputer-Based System Design (EEC 172)+ Managed a four to five hour a week lab dealing with all aspects of embedded software development and hardware interfacing on the TI/Luminary Micro LM3S8962 microcontrollers.+ Worked with TI/Luminary Micro's StellarisWare and Keil ARM IDE design kits.+ Graded midterms and laboratory assignments.

Davis, California, Us

+ Selected the appropriate packages for short-term prototyping and long-term testing. This included making two bonding diagrams for a 223 pin PGA and a 304 pin SBGA.+ Designed the PCB layout for a custom interface board between the configuration FPGA and chip for short-term prototyping, and made final decisions over surface mount ICs and connectors.+ Coordinated the search for OSAT contractors that could do wire bonding onto fine pitched (78 µm (3.1 mil)) pad spacings and narrow pad openings (34x108 µm^2 (1.3x4.25 mil^2)).+ Within three days of receiving bare dies the manycore chip was determined fully operational.

Davis, California, Us

+ Led a team from concept to tape-out of a 1.2 GHz, 167-core, 39.4 mm^2 chip in nine months.+ Energy-efficiency: 200 billion operations per second at 1.3 V, dissipating 10 W (20 GOPS/W). Peak energy-efficiency: nearly 200 GOPS/W at 0.675 V (16-bit fused multiply-accumulate).+ Managed 10 M.S. and Ph.D. candidates working on the design and testing of IP blocks, per-core dynamic voltage and frequency scaling, and chip-level integration including global power grid and Vdd/Gnd/IO-ring construction, in addition to performing a hierarchical DRC/LVS.+ Designed and fabricated on an early 65 nm ST Microelectronics LP process run; managed CAD tool flow from RTL-to-GDSII including: Synopsys Design Compiler and Primetime, Cadence Encounter and Virtuoso, and Mentor Calibre; used Perl, Python, and Tcl to automate tasks.

Ph.D., Electrical And Computer Engineering

M.S., Electrical And Computer Engineering

B.S., Electrical And Computer Engineering

High School