Microprocessor Verification for IBM ZArchitecture and Security related development for IBM POWER processor line

Accelerated simulation based verification of POWER server microprocessors

Dissertation topic: "Harnessing Simulation Acceleration to Solve the Digital Design Verification Challenge"My research interests are speeding up core Electronic Design Automation(EDA) problems through the use of massively parallel multi-core platforms such as GPU's and enabling verification of large industrial-scale designs through semi-formal and simulation-based methods leveraging high-performance simulation.

Adopted an existing processor core checking solution (Instruction-By-Instruction checking) for accelerated simulation by intelligent collection of trace data. This checking solution is targeted for pre-silicon validation of upcoming IBM POWER processor design generation. This work has been published in DAC 2012 conference.

Project goal was to develop a high level power model for the fusion APU's (integrated CPU cores with a GPU on chip), which works at the granularity of driver API calls between the CPU and GPU and provides power estimate. The tool was used for design exploration.