Soc Design Verification Engineer
CurrentPerformed detailed functional verification of various on chip memories.Verified multiple analog modules including process, voltage and temperature sensors, POK, POR, temperature diode, voltage and thermal management.Responsible for verifying low power techniques such as isolation, switchable power domains and level shifters. This includes setting up and running power aware RTL simulations along with running Specman, Jasper and TCL checkers.Ownership of system level power management which includes verification of various low power modes.Responsible for setting verification goals and tracking power DV progress in terms of toggle and functional coverage.Involved in power aware bringup with boundary scan and emulation.Actively collaborate with library team, integration team and physical design team to have a comprehensive power verification strategy.Generated and maintained tests to verify the Power Sleep Controller. Debug done mostly using Simvision and Indago. Experienced in power estimation techniques using Joules and Voltus at both RTL and gate level. Primary owner to generate power numbers for multiple devices for idle and pbist scenarios.Familiarity with both CPF and UPF semantics. Knowledge of CLP flow development and UPF correctness check in RTL.
