1, Good experience of 10+ years in Analog & Mixed Signal IP's such as LDO, PLL, DDR and SERDES, Display Port layout design.2, Worked on various process nodes ranging from 3nm FINFET to 180nm CMOS Technologies.3, Worked with the process from foundries like SAMSUNG, TSMC, GLOBAL FOUNDRIES, INTEL, etc.4, worked with the PD team on family level integration.4, worked as a lead , handled projects such as LDO and JBIST, PLL, BGR, QUANTUM LAYOUTS.