Deepak George Email & Phone Number

Leuven, Flanders, Be

Leuven, Belgium

Singapore

Singapore

• Selected in the pioneer batch of patent examiners that established the patent search and examination unit at IPOS, received formal IP training at IP Academy Singapore, European Patent Office (EPO) and Japanese Patent Office (JPO).• Responsible for search and examination of ICT patent applications.• Responsible for drafting examiner guidelines and training subsequent batches of associate patent examiners in matters related to patentability and patentable subject matter.• Participated in bench-marking exercises with patent examiners from USPTO, JPO and the German Patent Office (DPMA).

Singapore

Project Manager:• Technical lead and project manager responsible for developing IP sub-systems in broadband digital subscriber line (xDSL) central office SOC, Mix-signal Gigabit Ethernet PHY chipset and safety sub-system for 32-bit automotive microcontrollers.• Resource planning and team setup. Lead multi-site, cross-functional teams located across Singapore, India, Germany and Austria, through all stages of the development cycle from initial concept to production ramp-up and customer support.• Created, tracked and maintained project plans and risk management tables.• Provided periodic status updates to senior management.• Regularly trained and mentored front-end design engineers and university interns.ASIC Designer:• Specialized in designing power and area optimized hardware accelerator architectures for digital signal processing (DSP), network processors, Ethernet switch/PHY, AFE mix-signal module integration and automotive micro-controllers. • Support xDSL and long reach ethernet standardization process.• HW Languages: VHDL, Verilog, System Verilog, C, Matlab-m, Specman-e, Perl, tcl.• HW/SW Tools: Synopsys-DC and Primetime, Cadence Incisive, Modelsim, Formality, CVE, Smartbits, IKOS, Palladium.

Singapore

Singapore

Msc (Signal Processing), Digital Signal Processing

B.E, Electronics Design And Technology