Deepak Sharma Email & Phone Number

Tokyo, Japan

Tokyo, Japan

Supervisor: Prof. Masaharu KobayashiResponsibilities:- Conducted independent research on the design and development of FeFET-based memory devices using novel 2D materials such as MoS2, WSe2, WS2, and h-BN.- Optimized the production process of 2D materials, leading to improved material quality and better process yield.- Investigated the ambipolar conductivity of 2D materials and optimized the write/erase performance.Achievements and Outcomes:- Developed over 20 successful devices, demonstrating proficiency in device fabrication and characterization.- Identified Ni/Au electrodes as the optimal choice for achieving ambipolarity in FeFETs through collaboration with researchers from AIST.- Contributed to the optimization of Metal/2D Material interfaces, leading to improved performance of FeFETs.- Made significant contributions to the field of FeFET-based memory devices using 2D materials.Gained:Independent research, Expertise in device fabrication and characterization, Process optimization, Collaboration and teamwork, Problem-solving and analytical skills

Bengaluru, Karnataka, India

Manager: Mr. Tushar PandeyResponsibilities:- Worked collaboratively in a team environment to develop and model high-speed I/O interfaces and package characteristics using the IBIS methodology.- Increased team throughput by creating over 100 IBIS models for use in Signal Integrity (SI) simulations.- Proactively identified, isolated, and resolved complex problems related to SI simulation, demonstrating strong problem-solving ability.- Collaborated with the team to improve model performance and efficiency, and resolved SI-related issues.- Correlated SI simulation and timing analysis with model measurements to complete four projects successfully.- Generated IBIS reports to deliver model measurements and facilitate project analysis.Achievements and Outcomes:- Developed over 100 IBIS models, increasing team throughput and contributing to successful project completion.- Resolved complex SI-related problems and improved model performance and efficiency, resulting in accurate SI simulation and timing analysis.- Correlated SI simulation and timing analysis with model measurements to complete four successful projects.- Built and maintained long-term, mutually beneficial relationships with clients, establishing trust and becoming their go-to resource.Gained: Proficient in the IBIS methodology and SI simulation, Collaborative team player with excellent communication and interpersonal skills, Detail-oriented with exceptional project management and organizational skills.

Mumbai, Maharashtra, India

Supervisor: Prof. Bhaskaran MuralidharanResponsibilities and Achievements:- Researched and implemented a material modeling strategy to device design, resulting in a 30% savings in project budget and reduced costs for growth and fabrication of materials.- Developed band-structure models for Type-II Superlattice Infrared Photodetector using concept of Solid-State Physics and NEGF Methodology based on Quantum-Mechanics.- Implemented the superlattice band structure of bulk InAs and GaSb using an 8-band k.p method with ISRO scientists, boosting the spectral responsivity from 3μm to 30μm.Gained:Expertise in material modeling and design strategy, Knowledge of k.p Hamiltonian Matrix computation and atomistic Non-Equilibrium Green’s Function integration, Ability to propose efficient and optimized designs for specific frequency regimes

Bengaluru, Karnataka, India

Supervisor: Navakanta BhatBachelor Thesis: Steep Slope Sub-Thermionic Conduction in MoS2 FET with a Tunable Transport. Responsibilites and Achievements:- Conducted multiple experiments as a researcher, resulting in the development of a steep slope tunable MoS2 FET.- Developed a novel low power transistor with 2D Material - MoS2 by adopting a T-Shaped Gate design strategy resulting in steep switching (34mV/dec) and high field effect mobility (84.3 cm2V-1s-1).- Fabricated and simulated a dual-gated multilayer MoS2 FET with independent gate control, an optimized Schottky Contact, and a tunable current transport mechanism.- Demonstrated low power consumption and high performance through characterization and TCAD simulation with a correlation of over 85% between modeled data and results.- Published the research findings in the IEEE Transactions on Nanotechnology, indicating the ability to communicate technical work effectively.Gained:Proficient in experimental techniques, including device fabrication and characterization, Expertise in TCAD simulations, Knowledge of 2D materials and their electronic properties, Ability to analyze and interpret data accurately and efficiently, Excellent technical writing and communication skills.

Jabalpur, Madhya Pradesh, India

Supervisor: Prof. Pravin Kondekar and Late Dr. Dheeraj SharmaResponsibilities and Achievements:-Designed energy-efficient FETs for high-speed logic devices using TCAD and physical modeling techniques-Investigated gate metal work function, high-k dielectric, and novel semiconductor materials to improve the subthreshold characteristics of Tunnel FETs-Implemented Poisson and Schrodinger equations based framework for simulation of emerging nanoelectronics devices in TCAD (Silvaco and Sentaurus)- Simulated various types of FETs using the framework to observe the optimized device structure and material process for obtaining steeper switching characteristics (SS < 60mV/decade)- Coordinated and collaborated with Principal Investigators for project proposal, planning, and execution- Published research articles in international journals and presented research papers at international conferences.Gained: Expertise in TCAD simulation, Proficiency in project proposal, planning, and execution, Ability of technical documentation and presenting research papers.

Master Of Science - Ms, Electrical Engineering And Information Systems

Bachelor Of Technology - Btech, Electronics And Communications Engineering

Activities and Societies: Electronics, Robotics, Astronomy