Part of a small debug team (Manual Debug Team, MDT) that handles fast paced, high pressure and critical SoC-level debug for post-silicon sightings from the HW side for Meteor Lake and Arrow Lake client CPUs. I am involved in active hands-on functional debug on validation platforms and leading sessions to triage & debug system failures, run experiments & collect data, engage a broad set of experts, and drive issues to root-cause. The issues we look at span the entire SoC and can involve coherent, non coherent and power management flows, across various IPs, mainband and sideband fabrics, and involve complex HW and FW/SW interactions. I work closely with pre-silicon design & validation, architecture and SW/driver experts to understand interactions between various IP, SoC and SW/FW agents. I am also involved in defining workarounds to ungate silicon execution and feeding post silicon learnings back to pre silicon design.

As part of a rotation in the client CPU Power Management FW development team, I leveraged the FW exposure gained from post-silicon debug and pre-silicon design to code power management FW features directly. As part of the FW team, I’ve been supporting debug of various post silicon issues in or around PM FW flows and making fixes & workarounds for Arrow Lake CPUs, as well as coding new FW features for next gen Intel CPUs.

Worked on pre-silicon RTL design and integration of tracing and triggering IPs as part of the Design for Debug (DFD) Team, for Cannon Lake desktop, Tiger Lake and Meteor Lake client CPUs. The DFD team is responsible for integrating various debug IPs such as signal-level trace fabric, packetized trace fabric, protocol specific trace sources, trigger blocks and trace aggregators into client SoCs. Additionally, the team designs IP-blocks to bridge the gap between off-the-shelf IPs and SoC requirements. The team also works closely with architecture to define power management flows for these debug IPs according to their post silicon usage models. As part of the team, I was also responsible for delivering the RTL and UPF intent of the design and running quality checks like RTL lint, VCLP, Spyglass CDC and Spyglass RDC. I also had to work with STA and backend design to ensure the design met timing and synthesis requirements. In addition, I worked with the post-silicon dfx team to enable various debug tools.

Wrote Perl scripts to download websites, parse them, extract and upload relevant/useful information into multiple MySQL databases.

Physics 104 - Spring 2015Physics 103 - Fall 2015

Member of System Performance Architecture (SPA) at Samsung Austin Research Center (SARC). Within SPA, worked in Performance Architecture Veracity Evaluation (PAVE) team, responsible for Performance Correlation and Feature Correlation. Responsibilities included developing/improving RTL and performance model infrastructure/tools for system level mobile SoC.

ASIC Design Engineer in Nvidia Tegra. Core member of the XUSB Team. (XUSB deals with xHCI, USB2, USB3 and HSIC protocols). Worked on controller verification.

Worked on chip-level post-silicon verification.Worked on MATLAB based signal processing.

Worked on GPS/Mobile Communication related robustness problems.