Deepthi Dasari Email & Phone Number

San Jose, Ca, Us

Santa Clara, Ca, Us

Cupertino, California, Us

Cupertino, California, Us

Cupertino, California, Us

Santa Clara, California, Us

Architecture Validation of next generation multi-core CPU: o Trained on IA-32, IA-64 architectures, P6 microarchitecture, Memory Hierarchy, Multi Level Caches, Cache Coherency, Intel internal architecture simulator tools and verification environment o Reset Validation of multi-core CPU at Full Chip Level. o Generation of tests targeting Multi-Core, Multi-threaded functionality using Intel’s internal native instruction test generator tools. o Development of test plan and generation of tests targeting the new instructions supported by the processor. o Ownership of Full Chip regressions, Debug and triage of failing Full Chip test cases in Architecture Simulator based co-simulation environment to find RTL failures/ Architecture Simulator issues. o PERL scripting for Post-processing of Full Chip regression results.Post-Silicon Validation of next generation multi-core CPU: o Addressing speed issues by identification of speed-paths in the design. o Fault Isolation and Analysis of Vmin failures and Scan chain/Capture failures. o Stop clock validation using Test Access Port features.

Dallas, Tx, Us

Project I - Single Chip baseband 3G solution for NOKIA o Responsible for validation of SoC using ‘C’ testcases and co-simulation environment of TI. o Module Level Verification of PSCON(Power State CONtroller) module  Test Plan Writing and Functional/Code Coverage  System Verilog based test stimulus generator  Formal Verification using PSL (Property Specific Language) o Validation of G12 module (Image Processor) using C testcases. o Power Aware setup and simulations at RTL and GATE level using Modelsim.Project II - Connectivity SOC project for NOKIA (Bluetooth, FM, GPS) o Gate Level validation using C and e testcases. o Power Aware simulations using Modelsim

Masters, Computer Engineering

B.Tech, Electronics And Communications