Hardware Designer
Current• Captured schematic designs using Cadence Capture CIS and Design Entry HDL. • Developed high-speed digital prototypes with 10G-T1, XFI, PCIe Gen4.• Evaluated timing, signal integrity, stack-up, and thermal requirements on multilayer PCBs.• Selected, simulated and verified SMPS solutions, including Bode Plot analysis, Phase Margin, Gain Margin, load step transient response, and output ripple for single and multi-phase regulators. • Designed and verified complex clock trees, including RSS clock jitter analysis, PCIE REFCLK requirements, synchronization, clock synthesizers and buffers, High-PSRR LDO design for clocking. • Debugged complex hardware issues involving power, clocks, resets, signal integrity and other issues in systems with technology including FPGA RFSoCs, QSFP ethernet (fiber and DAC), HDMI, and NVMe.• Generated Configuration files for devices including Gen4 PFX PCIE Switches in Chiplink, timing devices (Skyworks CBPro, SiTime Time Master, Cascade, Renesas Timing Commander, Texas Instruments TICS), PMIC devices (Analog LTPowerplay, LTPowerCAD, Texas Instruments Fusion).• Designed scripts for bringup and functional testing using Bash, Python, etc.
