Acquired a deep understanding of SystemVerilog and verification methodologies, particularly UVM, along with deep knowledge in core subjects like digital electronics.Developed strong proficiency with EDA tools such as Synopsys VCS, Verdi, and Mentor Graphics QuestaSim.Gained hands-on experience on multiple verification projects, including the verification of four 4096x64 RAM SoCs and a 1x3 Router.

Project: CXL IPFor a given IP worked on writing and modifying different sequences and testcases.Helped in debugging RTL code using Synopsys Verdi tool.Implemented Functional Coverage to insure testing coverage.Regression support to collect the coverage.Worked on script to automate the regression process.