Please complete the CAPTCHA to continue
@microsoft.com
✓
LinkedIn matched
A concise factual answer block for searchers comparing this professional profile.
Dev Desai is listed as Senior FPGA Design Engineer at Microsoft at Microsoft, a company with 10 employees, based in Greater Seattle Area, United States, United States. AeroLeads shows a work email signal at microsoft.com and a matched LinkedIn profile for Dev Desai.
Dev Desai previously worked as Senior Hardware Design Engineer at Microsoft and Hardware Development Engineer at Microsoft. Dev Desai holds Master Of Science (Ms), Electrical And Electronics Engineering from San José State University.
This section adds company-level context without repeating Dev Desai's masked contact details.
AeroLeads found 2 current-domain work email signals for Dev Desai. Compare company email patterns before reaching out.
As an Senior FPGA Design Engineer in the Microsoft Azure Networking team for the past six years, I have been at the forefront of integrating cutting-edge technology into our data centers. My work primarily focuses on developing and deploying high-performance FPGA-based solutions to enhance network functionality and security.* Played a pivotal role in the SmartNIC project, contributing to the design and implementation of FPGA solutions that offload network functions, improving latency, throughput, and CPU utilization.* Utilized Agile methodologies to collaborate closely with both hardware and software teams, ensuring rapid development and deployment cycles.* Focused on integrating SDN offload capabilities, enhancing the programmability and flexibility of our virtual networking features .* Engineered FPGA-based encryption modules to secure virtual networks, ensuring robust protection of data in transit without compromising performance.Responsibilities: * Our team is responsible for the deployment of FPGA solutions across Azure's global data centers, ensuring seamless integration with existing infrastructure. Actively participate in on-call rotations to tackle and resolve production issues, leveraging deep technical knowledge to maintain high availability and performance of network services.Achievements:* Successfully contributed to hyperscale deployment of FPGA Designs on millions of clusters, addressing numerous technical and logistical challenges to achieve seamless integration and scalability .My tenure at Microsoft has honed my expertise in FPGA development and deployment, equipping me with a unique skill set that bridges hardware performance with software flexibility. I am passionate about driving innovation in cloud networking, Artificial Intelligence and computer architecture and look forward to contributing to more groundbreaking projects in the future.I would love to connect with computer architecture enthusiast and talk more about future technologies :)
Listed skills include C, Verilog, Microsoft Excel, Matlab, and 33 others.
Company context helps verify the profile and gives searchers a useful next step.
A career timeline built from the work history available for this profile.
Redmond, Washington, US
As an FPGA Engineer on the Microsoft Azure Networking team for the past five years, I have been at the forefront of integrating cutting-edge technology into our data centers. My work primarily focuses on developing and deploying high-performance FPGA-based solutions to enhance network functionality and security.* Played a pivotal role in the SmartNIC.
Redmond, Washington, US
Azure Networking(FPGA Team)Azure Accelerated Networking(https://www.microsoft.com/en-us/research/uploads/prod/2018/03/Azure_SmartNIC_NSDI_2018.pdf)
Sunnyvale, California, US
**Hardware Development Engineer | Chelsio Communications**- Contributed to the hardware development team for the next-generation ASIC Networking Chip.- Delivered several initial design implementations, gaining valuable experience and insights in the early stages of my career.- Collaborated with a team of exceptional engineers, learning extensively from.
**Design and Verification Engineer | SSR Labs**- Designed a neural network chip for AI applications.- Collaborated closely with the verification and design teams to ensure seamless integration and functionality.- Developed the UVM testbench for the neural network chip block, enhancing verification efficiency and accuracy.
San Jose, California, US
- Collaborated closely with the eFPGA Architecture Design Team.- Contributed to the Testing Team for AURORA software (eFPGA SoC integration tool), providing critical feedback on STA and Place & Route tools and recommending enhancements for user flexibility.- Presented ideas for new FPGA architectures optimized for DSP applications, data centers, and neural.
Vadodara, Gujarat, IN
Matrix is a leading manufacturer of world class telecom and security solutions. These versatile, feature-rich and reliable solutions are built with latest hardware and software technologies. I worked on a project which is based on GSM, VoIP and EPABX Based Device Control.
Other employees you can reach at microsoft.com. View company contacts for 10 employees →
Peter Manchidi
Colleague at Microsoft
Pretoria, Gauteng, South Africa, South Africa
View →
FK
Fatim Keita
Colleague at Microsoft
Bamako, Mali, Mali
View →
MM
Md Mohiuddin All Mahmud Shadi
Colleague at Microsoft
Dhaka, Dhaka, Bangladesh, Bangladesh
View →
TJ
Tate James
Colleague at Microsoft
London, England, United Kingdom, United Kingdom
View →
TN
Trisha Naskar
Colleague at Microsoft
Kolkata, West Bengal, India, India
View →
CG
Camelia Grannum
Colleague at Microsoft
Edmonton, Alberta, Canada, Canada
View →
أا
أمي الغالية
Colleague at Microsoft
Casablanca, Casablanca-Settat, Morocco, Morocco
View →
JM
Jeffery Mei
Colleague at Microsoft
Shanghai, Shanghai, China, China
View →
AR
Aryan Raj
Colleague at Microsoft
Vaishali, Bihar, India, India
View →
KS
Kevin Souza
Colleague at Microsoft
Albany, New York Metropolitan Area, United States
View →
Quick answers generated from the profile data available on this page.
Dev Desai works for Microsoft.
Dev Desai is listed as Senior FPGA Design Engineer at Microsoft at Microsoft.
AeroLeads has found 2 work email signals at @microsoft.com for Dev Desai at Microsoft.
Dev Desai is based in Greater Seattle Area, United States, United States while working with Microsoft.
Dev Desai has worked for Microsoft, Chelsio Communications, Scalable Systems Research Labs Inc., Quicklogic, and Matrix Comsec.
Dev Desai's colleagues at Microsoft include Peter Manchidi, Fatim Keita, Md Mohiuddin All Mahmud Shadi, Tate James, and Trisha Naskar.
You can use AeroLeads to view verified contact signals for Dev Desai at Microsoft, including work email, phone, and LinkedIn data when available.
Dev Desai holds Master Of Science (Ms), Electrical And Electronics Engineering from San José State University.
Dev Desai is listed with skills including C, Verilog, Microsoft Excel, Matlab, Microsoft Office, Microsoft Word, C++, and System Verilog.
Search by job title, company, industry, location, and seniority. Export verified B2B contact data when you need it.
Start free trial Search contacts