Deyan Chen Email & Phone Number

Ottawa, Ontario, Canada

Shanghai, China

Device development for sensor application

Shanghai City, China

TCAD group: Take over CIS/Flash/Power device development.

Singapore

1. Working on state of the art TCAD simulation to support TD and develop novel technology and power device: calibrate the process and device model to predict current device performance, optimize process to shorten manufacturing cycle time to market. 2. Major achievement: 0.18/0.13um 30V 60V 85V Lower Rdson process design especially on device reliability improvement; 65nm/40nm EDMOS fundamental leakage reduction; 3. Manage the TCAD-HV group on VAS projects: responsible for projects management and problem solving.

Shanghai City, China

1. 40nm GP logic process support: well isolation simulation implementation; trade off the Cov and Ion/Ioff curve by device structure optimization and new impurity(Ge, C…) for USJ consideration, stress for device channel mobility enhancement. 2. 0.35um UMOS technology development: optimize process including well formation and epitaxial layer information and use FFLR (Floating Field Limiting Rings) technique to achieve customer’s target (Rds(on), BVDss). 3. 0.18um LDMOS device development in PMIC4 project: investigated Double-Hump phenomenon for Isub curve; Reduce Surface Field (RESURF) by drift region optimization to improve operation voltage, design a novel structure having the similar characteristic with mask sharing to reduce the cost and to compile patent. 4. Bipolar and MVNMOS performance improvement in PMIC4 project: optimize process to reduce built-in potential between base and emitter and Vt Roll-off curve for NMOS; co-work with RE to pass the HCI testing by tuning LDD formation and enhance the production yield. 5. Responsible for diode fabrication process flow design for 0.13um PCM project: optimize the NBL doping profile to get higher current with lower leakage. 6. Collaborated with DFM/SPICE Modeling group and successfully implemented WPE simulation in 3D mode, be considered into a design verification system for 90nm Logic Technology. 7. Support PIE to built up advanced process, evaluates feasibility and shorten the fabrication cycle time, such as: MEMS and BOSCH project. 8. Trained and supervised several new engineers and designers on TCAD application.

Shanghai City, China

1. Responsible for active and passive device’s spice model extraction with BSIM3 tools for all technologies. Interacted with process integrators and designers to resolve all device related issues and provide characterization support for process development. 2. benchmarked BTA 1/f noise measurement system. worked on 1/f noised measurement procedure and validation. Performed 1/f noised characterization and modeling for various technologies. 3. Simulate some sub-circuits to verify the spice model convergence and continuation, ensure its quality in design system. 4. Cell model extraction for 0.18um EEPROM OTP Flash memory. 5. Collaborated with NTIH group to perform NROM/SONOS device characterization analysis: Using software (VEE/RIFLE) to evaluate cycle time, data retention and endurance. 6. Write 4 patents about NROM array to improve its disturbance and reliability while be programmed and erased.7. Investigated other flash memory: Split-Gate Flash, EEPROM, Pflash, PCM, RRAM, etc.

Master'S Degree, Condensed State Physics

Bachelor'S Degree, Physics